Patents by Inventor Shing Luo
Shing Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9360401Abstract: The present invention provides a sample stack structure with multiple layers. The sample stack structure has at least a substrate, an adhesive layer and a target layer. The target layer is directly sandwiched between the substrate and the adhesive layer.Type: GrantFiled: September 24, 2014Date of Patent: June 7, 2016Assignee: INOTERA MEMORIES, INC.Inventors: Jian-Shing Luo, Hsiu-Ting Lee
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Publication number: 20160084742Abstract: The present invention provides a sample stack structure with multiple layers. The sample stack structure has at least a substrate, an adhesive layer and a target layer. The target layer is directly sandwiched between the substrate and the adhesive layer.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Jian-Shing Luo, Hsiu-Ting Lee
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Patent number: 8481968Abstract: A method for preparing an electron microscope specimen is provided. The method includes providing a wafer sample with an analysis region disposed thereon. A dicing process is performed to cut a sample piece from the wafer sample. The sample piece includes a target pillar structure wherein the analysis region is located on a top portion of the target pillar structure. A thinning process is performed to thin the top portion of the target pillar structure. The invention further provides an electron microscope specimen and a method of forming a 3D image.Type: GrantFiled: November 29, 2010Date of Patent: July 9, 2013Assignee: Inotera Memories, Inc.Inventors: Jian-Shing Luo, Wen-Shan Hsu
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Publication number: 20110291008Abstract: A method for preparing an electron microscope specimen is provided. The method includes providing a wafer sample with an analysis region disposed thereon. A dicing process is performed to cut a sample piece from the wafer sample. The sample piece includes a target pillar structure wherein the analysis region is located on a top portion of the target pillar structure. A thinning process is performed to thin the top portion of the target pillar structure. The invention further provides an electron microscope specimen and a method of forming a 3D image.Type: ApplicationFiled: November 29, 2010Publication date: December 1, 2011Inventors: Jian-Shing Luo, Wen-Shan Hsu
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Patent number: 7939906Abstract: A manufacturing method for an electron tomography specimen with embedded fiducial markers includes the following steps. A chip of wafer is provided. The chip includes at least one inspecting area. At least one trench is produced beside the inspecting area. A liquid with the markers is filled into the trenches. A first protection layer is coated on the chip, and then a second protection layer is deposited on the first protection layer. Therefore, the markers can be embedded into the electron tomography specimen. The embedded markers can improve the alignment process, due to those embedded markers are easily tracked during feature tracking procedure. In addition, our novel invention also successfully provides a modified version of the technique to deposit gold beads onto TEM pillar samples for much improved 3D reconstruction.Type: GrantFiled: May 26, 2009Date of Patent: May 10, 2011Assignee: Inotera Memories, Inc.Inventors: Jian-Shing Luo, Chia-Chi Huang
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Publication number: 20100084555Abstract: A manufacturing method for an electron tomography specimen with embedded fiducial markers includes the following steps. A chip of wafer is provided. The chip includes at least one inspecting area. At least one trench is produced beside the inspecting area. A liquid with the markers is filled into the trenches. A first protection layer is coated on the chip, and then a second protection layer is deposited on the first protection layer. Therefore, the markers can be embedded into the electron tomography specimen. The embedded markers can improve the alignment process, due to those embedded markers are easily tracked during feature tracking procedure. In addition, our novel invention also successfully provides a modified version of the technique to deposit gold beads onto TEM pillar samples for much improved 3D reconstruction.Type: ApplicationFiled: May 26, 2009Publication date: April 8, 2010Applicant: INOTERA MEMORIES, INC.Inventors: JIAN-SHING LUO, CHIA-CHI HUANG
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Patent number: 7538322Abstract: A method of fabricating sample lamella for transmission electron microscopy (TEM) analysis is provided. A waiting-examination sample having an analysis target on the top surface of that is offered, and at least a mark around the analysis target is defined. A covering layer is covered on the top surface of waiting-examination sample. A holder is attached on the covering layer. A backside polishing process is performed to remove a portion of the waiting-examination sample until the mark is visible under the optical microscopy from the bottom surface of waiting-examination sample. An in-situ lift-out step is performed to pick up a thin membrane containing the analysis target and serve as the sample for TEM analysis.Type: GrantFiled: November 3, 2006Date of Patent: May 26, 2009Assignee: Inotera Memories, Inc.Inventors: Jian-Shing Luo, Lang-Yu Huang
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Publication number: 20080054179Abstract: A method of fabricating sample lamella for transmission electron microscopy (TEM) analysis is provided. A waiting-examination sample having an analysis target on the top surface of that is offered, and at least a mark around the analysis target is defined. A covering layer is covered on the top surface of waiting-examination sample. A holder is attached on the covering layer. A backside polishing process is performed to remove a portion of the waiting-examination sample until the mark is visible under the optical microscopy from the bottom surface of waiting-examination sample. An in-situ lift-out step is performed to pick up a thin membrane containing the analysis target and serve as the sample for TEM analysis.Type: ApplicationFiled: November 3, 2006Publication date: March 6, 2008Applicant: INOTERA MEMORIES, INC.Inventors: Jian-Shing Luo, Lang-Yu Huang
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Patent number: 7319583Abstract: An electronic device includes first and second housings which are pivoted to each other, and a spring-biased stopper mounted movably on an upper wall of the first housing. The stopper is movable in a transverse direction relative to the upper wall between an engaging position, in which the stopper projects outwardly of the first housing through the upper wall and engages the second housing, and a second position, in which the stopper is received in the first housing and disengages from the second housing.Type: GrantFiled: July 5, 2006Date of Patent: January 15, 2008Assignee: Wistron CorporationInventors: Hua-Chung Tseng, Shu-Hsien Chu, Cheng-Shing Luo, Chu-Hsian Chian, Yang-Po Chiu
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Publication number: 20070187813Abstract: A semiconductor device comprises a substrate, a patterned metal conductor layer over the substrate, and a passivation layer. The passivation layer may comprise a UV blocking, protection layer, over at least a portion of the substrate and patterned metal conductor layers, and a separation layer between the patterned metal conductor layer and the UV protection layer. The passivation layer may also comprise a gap-filling, hydrogen-blocking layer over the substrate, the patterned metal conductor layer and any UV protection layer.Type: ApplicationFiled: February 10, 2006Publication date: August 16, 2007Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Lee Chen, Shing Luo, Chin Su
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Publication number: 20070190806Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a patterned metal conductor layer. To provide UV blocking, an overlying separation layer is formed over the substrate, and a UV blocking layer of silicon enriched oxide is formed over the separation layer. The UV blocking layer has a silicon atomic concentration sufficient for ultraviolet blocking. A gap-filling, hydrogen-blocking layer may be formed over the semiconductor substrate, and any the UV blocking layer, to prevent hydrogen from passing therethrough.Type: ApplicationFiled: February 10, 2006Publication date: August 16, 2007Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Lee Chen, Shing Luo, Chin Su
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Publication number: 20060278778Abstract: An electronic device includes first and second housings which are pivoted to each other, and a spring-biased stopper mounted movably on an upper wall of the first housing. The stopper is movable in a transverse direction relative to the upper wall between an engaging position, in which the stopper projects outwardly of the first housing through the upper wall and engages the second housing, and a second position, in which the stopper is received in the first housing and disengages from the second housing.Type: ApplicationFiled: July 5, 2006Publication date: December 14, 2006Inventors: Hua-Chung Tseng, Shu-Hsien Chu, Cheng-Shing Luo, Chu-Hsian Chian, Yang-Po Chiu
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Publication number: 20060278787Abstract: An electronic device includes first and second housings which are pivoted to each other, and a spring-biased stopper mounted movably on an upper wall of the first housing. The stopper is movable in a transverse direction relative to the upper wall between an engaging position, in which the stopper projects outwardly of the first housing through the upper wall and engages the second housing, and a second position, in which the stopper is received in the first housing and disengages from the second housing.Type: ApplicationFiled: July 5, 2006Publication date: December 14, 2006Inventors: Hua-Chung Tseng, Shu-Hsien Chu, Cheng-Shing Luo, Chu-Hsian Chian, Yang-Po Chiu
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Patent number: 7100876Abstract: An electronic device includes first and second housings which are pivoted to each other, and a spring-biased stopper mounted movably on an upper wall of the first housing. The stopper is movable in a transverse direction relative to the upper wall between an engaging position, in which the stopper projects outwardly of the first housing through the upper wall and engages the second housing, and a second position, in which the stopper is received in the first housing and disengages from the second housing.Type: GrantFiled: September 12, 2003Date of Patent: September 5, 2006Assignee: Wistron CorporationInventors: Hua-Chung Tseng, Shu-Hsien Chu, Cheng-Shing Luo, Chu-Hsian Chian, Yang-Po Chiu
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Publication number: 20060071301Abstract: A light absorption layer for use in fabricating semiconductor devices is provided with a high Si concentration. For example, a semiconductor device comprises a substrate and an Si-rich dielectric light absorption layer, such as an SiON or SiOX layer having an Si concentration of at least 68%. A second dielectric antireflective coating layer is optionally formed over the Si-rich dielectric light absorption layer.Type: ApplicationFiled: October 6, 2004Publication date: April 6, 2006Inventors: Shing Luo, Chin Su
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Publication number: 20040090740Abstract: An electronic device includes first and second housings which are pivoted to each other, and a spring-biased stopper mounted movably on an upper wall of the first housing. The stopper is movable in a transverse direction relative to the upper wall between an engaging position, in which the stopper projects outwardly of the first housing through the upper wall and engages the second housing, and a second position, in which the stopper is received in the first housing and disengages from the second housing.Type: ApplicationFiled: September 12, 2003Publication date: May 13, 2004Applicant: Wistron CorporationInventors: Hua-Chung Tseng, Shu-Hsien Chu, Cheng-Shing Luo, Chu-Hsian Chian, Yang-Po Chiu