Abstract: An interposer for a semiconductor package structure includes a base substrate, a plurality of passive devices formed on the base substrate, and an identification (ID) code. The base substrate includes a first surface and an opposite second surface. The ID code is formed on the first surface or the second surface of the base substrate.

Abstract: A device under test (DUT) array provides defect information rapidly and systematically. The DUT array includes a plurality of test units arranged in a matrix, a plurality of bit lines and a plurality of word lines. Each test unit has a first terminal and a second terminal. Each second terminal of the test unit is electrically connected to a ground point. The first terminals of the test units are electrically connected to the bit lines. The word lines are coupled to the test units. Defects in the each test unit can be identified by providing voltages to the bit lines and the word lines. Accordingly, defects in various devices of an integrated circuit can be detected rapidly and systematically by applying signals to the DUT array.

Abstract: A test system provides defect information rapidly and systematically. The test system includes a plurality of test units arranged in a matrix, a plurality of bit lines and a plurality of word lines. Each test unit has a first terminal and a second terminal. Each second terminal of the test unit is electrically connected to a ground point. The first terminals of the test units are electrically connected to the bit lines. The word lines are coupled to the test units. Defects in the each test unit can be identified by providing voltages to the bit lines and the word lines. Accordingly, defects in various devices of an integrated circuit can be detected rapidly and systematically by applying signals to the test system.

Abstract: A method of fabricating an anti-fuse includes firstly forming a dielectric layer on a substrate having a first conductive type. Next, a conductive layer is formed on the dielectric layer. A first ion implantation process is then performed, such that the conductive layer has the first conductive type. Thereafter, the conductive layer and the dielectric layer are patterned to form a gate and a gate dielectric layer. The gate and the gate dielectric layer together construct a gate structure. Finally, two source/drain regions having a second conductive type are formed in the substrate at respective sides of the gate. Besides, a method of programming an anti-fuse includes firstly applying a voltage to a gate to break down a gate dielectric layer. The gate and a substrate are then electrically conducted or a P/N forward bias is then formed in a P/N junction after the breakdown of the gate dielectric layer.

Abstract: An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions.

Abstract: An anti-fuse is formed with a transistor with a doped channel. The anti-fuse will not generate a non-linear current after the anti-fuse is blown. The anti-fuse is used in memory cells of one-time programmable (OTP) memory. The OTP memory utilizes a p-type transistor and an n-type transistor to program the anti-fuse. The anti-fuse has the doped channel, so a current will not flow through the p/n junction between the substrate and two doped regions of the anti-fuse to form a non-linear current after the anti-fuse is blown. Thus, the memory cells of the OTP memory can be programmed correctly.

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract: A bonding pad structure of semiconductor device having improved bondability is disclosed. The bonding pad structure uses at least one level comprising conductive islands and conductive plugs used as fasteners to prevent the bonding pad layer from peeling and cracking during the bonding process.

Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM.

Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines.

Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines.

Abstract: A method of manufacturing multiple metallic layered embedded ROM. A substrate has a memory cell region and a peripheral circuit region. A first gate and a first source/drain region are formed in the memory cell region. A second gate and a second source/drain region are formed in the peripheral circuit region. A first dielectric layer is formed over the substrate. A first contact is formed in the first dielectric layer in the periphery circuit region. A first patterned metallic layer that couple electrically with the first contact is formed in the peripheral circuit region. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer in the memory cell region is removed to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region. A via hole is formed in the second dielectric layer in the peripheral circuit region and a second contact opening is formed in the first dielectric layer in the memory cell region.

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs at a late stage in the manufacture of the ROM. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped N-type, gate electrodes are defined by photolithography, and then self-aligned silicide layers are formed on the gate electrodes. An insulating layer is then formed over the gate electrodes. Programming of the ROM is accomplished by forming a mask on the insulating layer and then implanting ions through openings in the mask, through the insulating layer and the silicide layer, and into the polysilicon layer.

Abstract: An improved metal oxide field effect transistor (MOSFET) provides an electro-static protection device with a high resistance to electro-static discharge. The electro-static discharge protection device has pre-gate heavily doped regions adjacent to the source and drain regions, where the pre-gate regions extend at least partially under the gate electrode. A single heavily doped pre-gate region may be provided for the MOSFET of the electro-static discharge protection circuit.

Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM.

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract: A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.

Abstract: An improved Read-Only-Memory (ROM) structure and a method of manufacturing said ROM device structure having an ultra-high-density of coded ROM cells, was achieved. The array of programmed ROM cells are composed of a single field effect transistor (FET) in each ROM cell. The improved ROM process utilizes the patterning of a ROM code insulating layer over each coded FET (cell) that is selected to remain in an off-state (nonconducting) when a gate voltage is applied. The remaining FETs (cells) have a thin gate oxide which switch to the on-state (conducting) when a gate voltage is applied. The thick ROM code insulating layer eliminates the need to code the FETs in the ROM memory cells by conventional high dose ion implantation. This eliminated the counter-doping of the buried bit lines by the implantation allowing for much tighter ground rules for the spacing between buried bit line.