Abstract: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.

Abstract: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.

Abstract: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.

Abstract: A circuit board and a fabrication method thereof. Providing the insulating layer with a first conductive layer formed thereon; wherein the insulating layer was formed on a core substrate with at least one patterned circuit layer thereon. A first resist layer is applied on a first conductive layer, forming first openings to expose the first conductive layer. A first patterned circuit layer, including conductive pads and traces, is formed in the first openings. A second resist layer is applied to cover the traces, and a conductive post is formed on each conductive pad. The first and second resist layers and the first conductive layer underneath the first resist layer are removed. A dielectric material layer is formed on the insulating layer with first patterned circuit layer, forming second openings to expose the conductive posts. A second conductive layer is formed on the dielectric material layer and in the second openings.

Abstract: An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through openings of the carrier board. Subsequently, cutting is processed via the through trenches. Thus, the space usage of the circuit board and the layout design are more efficient. Moreover, shaping time is also shortened.

Abstract: A circuit board structure and a method for fabricating the same are proposed. A plurality of conductive bumps and a first solder mask are formed on a carrier board, and the first solder mask is filled in the gaps between the conductive bumps and the conductive bumps are exposed. A first circuit layer and a first heat sink are formed on the first solder mask and the conductive bumps. A second heat sink is formed on the first heat sink, and a dielectric layer is formed on the first circuit layer and the first solder mask except the first and second heat sinks. A second circuit layer is formed on the dielectric layer and is electrically conductive to the first circuit layer. A third heat sink is formed on the second heat sink and a heat sink used for a chip mounting thereon is embedded in the dielectric layer. Therefore, the dimension of the circuit board is reduced and it is conformed to the dimension minimization progress of electronic devices.

Abstract: A structure of a circuit board and a method for fabricating the same are proposed. A first and a second dielectric layers are formed on a first and a second carrier boards respectively, and a first and a second circuit layers are formed on the first and second dielectric layer respectively. Then, between the first circuit layer of the first carrier board and the second circuit layer of the second carrier board is laminated a third dielectric layer, and thus the first circuit layer is embedded between the first and the third dielectric layers, and the second circuit layer is embedded between the second and the third dielectric layers. The two carrier boards are removed to form a core board with the first and the second circuit layers. Afterwards, a third and a fourth circuit layers are formed on the first and the second dielectric layers respectively.

Abstract: A method of fabricating electroplate solder on an organic circuit board for forming flip chip joints and board to board solder joints is disclosed. In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact pad. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer with at least an opening located at the pad is formed over the metal seed layer. A solder material is then formed in the opening by eletroplating. Finally, the resist and the metal seed layer beneath the resist are removed.

Abstract: A circuit board and a fabrication method thereof. Providing the insulating layer with a first conductive layer formed thereon; wherein the insulating layer was formed on a core substrate with at least one patterned circuit layer thereon. A first resist layer is applied on a first conductive layer, forming first openings to expose the first conductive layer. A first patterned circuit layer, including conductive pads and traces, is formed in the first openings. A second resist layer is applied to cover the traces, and a conductive post is formed on each conductive pad. The first and second resist layers and the first conductive layer underneath the first resist layer are removed. A dielectric material layer is formed on the insulating layer with first patterned circuit layer, forming second openings to expose the conductive posts. A second conductive layer is formed on the dielectric material layer and in the second openings.

Abstract: A method of fabricating electroplate solder on an organic circuit board for forming flip chip joints and board to board solder joints is disclosed. In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact pad. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer with at least an opening located at the pad is formed over the metal seed layer. A solder material is then formed in the opening by eletroplating. Finally, the resist and the metal seed layer beneath the resist are removed.