Abstract: A network sensing device is provided, which may include an active scheduling circuit and a sensor. The active scheduling circuit may operate regularly, and periodically generate a trigger signal. The sensor may include a power management circuit and a sensor circuit. The power management circuit may be coupled to the active scheduling circuit. The sensor circuit may be coupled to the power management circuit. The trigger signal may trigger the power management circuit, and the power management circuit may switch the sensor from a sleep mode to an active mode; the sensor circuit may collect the environmental information in the active mode, and the sensor may return to the sleep mode after the environmental information is saved.

Abstract: A wireless batch calibration apparatus, a wireless batch calibration system and a wireless batch calibration method. The wireless batch calibration apparatus includes a wireless transceiver, a processor circuit and a storage circuit. The wireless batch calibration apparatus receives a reference signal from a golden sample and a to-be-calibrated signal from each of a plurality of to-be-calibrated devices. The wireless batch calibration apparatus calculates the compensation value of each to-be-calibrated device, generating a compensation polynomial according to the compensation value and a calibration precision of each to-be-calibrated device, and establishes a calibration table. The wireless batch calibration apparatus writes the compensation polynomial and a setting bit back to each to-be-calibrated device, and completes the batch calibration of a plurality of to-be-calibrated devices.

Abstract: A wireless batch calibration apparatus, a wireless batch calibration system and a wireless batch calibration method. The wireless batch calibration apparatus includes a wireless transceiver, a processor circuit and a storage circuit. The wireless batch calibration apparatus receives a reference signal from a golden sample and a to-be-calibrated signal from each of a plurality of to-be-calibrated devices. The wireless batch calibration apparatus calculates the compensation value of each to-be-calibrated device, generating a compensation polynomial according to the compensation value and a calibration precision of each to-be-calibrated device, and establishes a calibration table. The wireless batch calibration apparatus writes the compensation polynomial and a setting bit back to each to-be-calibrated device, and completes the batch calibration of a plurality of to-be-calibrated devices.

Abstract: A very long instruction word (VLIW) processor and an apparatus with power management and a method of power management therefor are provided in consistent with the exemplary embodiments of the disclosure. The power management method includes the following steps. Valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package are rearranged to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor. Power reduction control is selectively performed on at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package according to the transcoded instruction package.

Abstract: A hybrid simulation model includes a real model, a bus interface and an acceleration model. The real model simulates a group of instructions. The acceleration model includes a trace generation unit, a trace replay unit, a selection unit, a snapshot generation and load unit and a virtual breakpoint control unit. The trace generation unit records at least one trace file of the real model in a first simulation. The trace replay unit reads and accordingly accesses the at least one trace file. The selection unit dynamically switches to perform a real simulation or a trace simulation. The snapshot generation and load unit generates at least one status snapshot file and loads the at least one status snapshot file to the real model in repeated simulations. The virtual breakpoint control unit controls the selection unit to switch between the trace simulation and the real simulation according to a virtual breakpoint.

Abstract: A hybrid simulation model includes a real model, a bus interface and an acceleration model. The real model simulates a group of instructions. The acceleration model includes a trace generation unit, a trace replay unit, a selection unit, a snapshot generation and load unit and a virtual breakpoint control unit. The trace generation unit records at least one trace file of the real model in a first simulation. The trace replay unit reads and accordingly accesses the at least one trace file. The selection unit dynamically switches to perform a real simulation or a trace simulation. The snapshot generation and load unit generates at least one status snapshot file and loads the at least one status snapshot file to the real model in repeated simulations. The virtual breakpoint control unit controls the selection unit to switch between the trace simulation and the real simulation according to a virtual breakpoint.

Abstract: A very long instruction word (VLIW) processor and an apparatus with power management and a method of power management therefor are provided in consistent with the exemplary embodiments of the disclosure. The power management method includes the following steps. Valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package are rearranged to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor. Power reduction control is selectively performed on at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package according to the transcoded instruction package.

Abstract: A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area of the memory cells of the ROM.

Abstract: A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area of the memory cells of the ROM.

Abstract: A built-in verification circuit having a circuit-under-test circuit, a test pattern generator, a bi-directional signal flow switch and three unidirectional, signal flow switches. The test pattern generator produces a testing pattern based on an input/output port order fault model. The bi-directional signal flow switch is positioned between the input terminal of the built-in verification circuit and the circuit-under-test circuit. The first unidirectional signal flow switch is positioned between the circuit-under-test circuit and the test pattern generator. The second unidirectional signal flow switch is positioned between the circuit-under-test circuit and the output terminal of the built-in verification circuit. The third unidirectional signal flow switch is positioned between the test pattern generator and the output terminal of the built-in verification circuit.

Abstract: There is disclosed a programmable memory emulator capable of emulating unspecified memory devices. A smart I/O interface is provided in the emulator for being programmed to conform to the interface specifications of different memory devices. An emulation look-ahead memory is employed to replace conventional two-port RAM. Furthermore, the memory of a host is utilized to emulate the functionality of system memory. Thus, the memory emulator is able to emulate various kinds of memory device, and the memory space is only restricted by the host.

Abstract: A method for representing arithmetic values on which arithmetic operations can be performed uses operands having a fixed number of bits. In a first step, a plurality of operands are stored in a memory, wherein each operand has a bit pattern representing a particular value. In a second step, a tag associated with each of the operands is also stored in the same or a different memory. Each of the tags has a tag value that indicates whether or not its associated operand represents an ordinary operand value or a special operand value. If the operand represents a special operand value, the tag value also indicates which of a predefined set of special operand values is represented by the associated operand. A result of an arithmetic operation can be generated by, in a first step, inputting at least a first operand and a first tag to an arithmetic section.

Abstract: A bidirectional shifter circuit is disclosed for shifting an inputted data word a chosen number of bit positions in either a first or a second chosen direction. The bidirectional shifter circuit is provided with a first bit-reversing circuit which receives an inputted data word. In response to choosing a first shift direction, the first bit-reversing circuit outputs the data word with the bits in their original order. In response to choosing the second shift direction, the first bit-reversing circuit outputs the data word with the bits in reverse order. A single-direction shifter circuit is provided which receives the data word outputted by the first bit-reversing circuit and shifts the received data word the chosen number of bit positions in the first direction.