Patents by Inventor Shingo Adachi
Shingo Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12719484Abstract: A first ring oscillator outputs a reference clock signal. A table acquirer acquires a control-value table representing a correspondence between time zones in which the first ring oscillator operates and division ratios of the reference clock signal. In accordance with the control-value table, a divider generates an RTC signal by changing a division ratio of the reference clock signal for each time zone in which the first ring oscillator operates. During execution of calibration of the control-value table, a second ring oscillator outputs a measurement clock signal that oscillates more accurately than the reference clock signal. A frequency measurer measures a frequency of the RTC signal based on the measurement clock signal. In a case in which a frequency of the RTC signal exceeds an allowable error, an update determiner updates at least part of division ratios in the control-value table.Type: GrantFiled: December 20, 2024Date of Patent: August 25, 2026Assignee: MEGACHIPS CORPORATIONInventors: Takeaki Komuro, Keisuke Kawanishi, Shingo Adachi
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Publication number: 20260145716Abstract: A timetable creating device according to an aspect of the present invention includes a schedule padding distribution deciding unit that distributes, to sections between stations, schedule padding in accordance with energy characteristics of traveling trains correlated with sections between stations, a change range storage unit that stores information of change ranges of arrival and departure times at each station, in which magnitude of effects on passenger convenience regarding changing trains is reflected, and a timetable creating unit that sets arrival and departure times at each station on the basis of the schedule padding distributed by the schedule padding distribution deciding unit. The schedule padding distribution deciding unit distributes, to sections between stations, schedule padding that enables the arrival and departure times at each station to be contained within the change range of arrival and departure times of each station.Type: ApplicationFiled: July 26, 2023Publication date: May 28, 2026Inventors: Yuhi TSUTSUMI, Shota KIMURA, Shingo ADACHI, Rieko OTSUKA, Tomoe TOMIYAMA, Yuuichi SATOU
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Publication number: 20260094227Abstract: In order to improve passenger satisfaction with a transportation service and to provide an operation plan creation means capable of reducing operating costs for a transportation service provider, an operation plan creation device comprises: a transportation leg network generation unit that generates transportation leg network information that defines each transportation leg of the transportation service; a cancellation determination unit that generates transportation leg cancellation possibility information that indicates whether or not cancellation of each transportation leg of the transportation service is possible; a travel route candidate determination unit that generates travel route candidate information that indicates a travel route candidate for each travel plan in passenger travel plan information; a people flow prediction unit that generates people flow prediction information that indicates a predicted people flow in the transportation service; and an operation plan generation unit that generates neType: ApplicationFiled: July 28, 2023Publication date: April 2, 2026Inventors: Eric Kui Shen TANG, Shunsuke UEDA, Yuki MAEKAWA, Hisanori TESHIMA, Shingo ADACHI
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Publication number: 20250306556Abstract: A first wire connects a control device to a cable, and supplies a first power signal provided by the control device to the cable. First and second nodes are provided in the first wire. A second wire connects a driving device to the cable, and supplies a first power signal transmitted from the cable to the driving device. Third and fourth nodes are provided in the second wire. A power supplier is connected to the first node and supplies a second power signal. A power receiver is connected to the third node, and provides a second power signal supplied by the power supplier to a detection device. A first communication circuitry is connected to the fourth node. A second communication circuitry is connected to the second node, and transmits a communication signal to or receives a communication signal from the first communication circuitry.Type: ApplicationFiled: March 21, 2025Publication date: October 2, 2025Applicant: MegaChips CorporationInventors: Yohei SATO, Masakazu TASHIBU, Shingo ADACHI
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Publication number: 20250274137Abstract: The present invention aims to suppress an increase in the size of a circuit configuration and achieve speed-up. The present invention is a successive-approximation ADC including: a CDAC consisting of a main capacitor bank consisting of a plurality of first capacitors and an auxiliary capacitor bank including a plurality of second capacitors to supply a corrected capacitance value to the first capacitors, a comparator configured to output a bit signal based on a capacitance redistribution signal output according to capacitance redistribution by the CDAC in response to an analog input signal, a logic circuit configured to output a digital output signal based on the bit signal, and a corrected capacitance value designation circuit configured to output a correction designation value that designates a corrected capacitance value to be supplied to the first capacitors.Type: ApplicationFiled: December 12, 2024Publication date: August 28, 2025Applicant: MegaChips CorporationInventors: Kazuhisa Hirai, Shingo Adachi
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Publication number: 20250253831Abstract: A first ring oscillator outputs a reference clock signal. A table acquirer acquires a control-value table representing a correspondence between time zones in which the first ring oscillator operates and division ratios of the reference clock signal. In accordance with the control-value table, a divider generates an RTC signal by changing a division ratio of the reference clock signal for each time zone in which the first ring oscillator operates. During execution of calibration of the control-value table, a second ring oscillator outputs a measurement clock signal that oscillates more accurately than the reference clock signal. A frequency measurer measures a frequency of the RTC signal based on the measurement clock signal. In a case in which a frequency of the RTC signal exceeds an allowable error, an update determiner updates at least part of division ratios in the control-value table.Type: ApplicationFiled: December 20, 2024Publication date: August 7, 2025Applicant: MegaChips CorporationInventors: Takeaki KOMURO, Keisuke KAWANISHI, Shingo ADACHI
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Publication number: 20250191100Abstract: A traffic service cooperation support system includes traffic service planning devices that manage traffic service plan information including transportation plan information between boarding and alighting points of a passenger, and a traffic service cooperation support device. The traffic service cooperation support device executes calculates a transportation service evaluation value for a passenger at a transfer point based on the traffic service plan information received from traffic service planning devices and passenger travel information by each traffic service, and transmits a target value of a transportation service of a transportation mode of a traffic service at the transfer point to the traffic service planning device of a traffic service through which a passenger gets on and off at the transfer point based on the evaluation value. The traffic service planning device controls the transportation mode based on the traffic service plan information generated based on the target value.Type: ApplicationFiled: March 17, 2022Publication date: June 12, 2025Applicant: HITACHI, LTD.Inventors: Tomoe TOMIYAMA, Tsuyoshi MINAKAWA, Yohei HASEGAWA, Shingo ADACHI, Keiji KIMURA, Miki YONEHARA
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Patent number: 11504917Abstract: A high viscosity material is discharged in the form of a continuous thread from an application nozzle toward an end of a workpiece and a space S on the side of the workpiece so that the high viscosity material in the form of the thread adheres to a front surface of the workpiece and the high viscosity material discharged in the form of the thread into the space on the side of the workpiece pivots around an edge of the workpiece to a back surface of the workpiece and adheres to the back surface of the workpiece. The high viscosity material can thus be applied to both the front and back surfaces of the workpiece in one step of discharging the high viscosity material only from the front surface side of the workpiece.Type: GrantFiled: March 3, 2021Date of Patent: November 22, 2022Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, ATLAS COPCO KKInventors: Shuhei Ogura, Hiroki Sugino, Tomohiko Sekiguchi, Shingo Adachi, Koki Kuwabara
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Publication number: 20210291462Abstract: A high viscosity material is discharged in the form of a continuous thread from an application nozzle toward an end of a workpiece and a space S on the side of the workpiece so that the high viscosity material in the form of the thread adheres to a front surface of the workpiece and the high viscosity material discharged in the form of the thread into the space on the side of the workpiece pivots around an edge of the workpiece to a back surface of the workpiece and adheres to the back surface of the workpiece. The high viscosity material can thus be applied to both the front and back surfaces of the workpiece in one step of discharging the high viscosity material only from the front surface side of the workpiece.Type: ApplicationFiled: March 3, 2021Publication date: September 23, 2021Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, ATLAS COPCO KKInventors: Shuhei OGURA, Hiroki SUGINO, Tomohiko SEKIGUCHI, Shingo ADACHI, Koki KUWABARA
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Patent number: 10135429Abstract: A clock correction device performs skew adjustment and duty correction of an input clock concurrently or in parallel. The clock correction device includes a correction circuit that performs skew adjustment of an input clock by analog control using a skew adjustment signal based on a phase difference between an output clock and a reference clock, receives a duty control signal, and performs duty correction of the input clock by digital control, a skew detection circuit that receives inputs of the output clock and the reference clock and, when only the reference clock is in a predetermined state, outputs a detection signal that changes to the predetermined state, an integration circuit that integrates the detection signal and generates a first voltage signal, and a comparator that compares the first voltage signal and a first reference signal to thereby generate the skew adjustment signal.Type: GrantFiled: March 22, 2017Date of Patent: November 20, 2018Assignee: MegaChips CorporationInventor: Shingo Adachi
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Publication number: 20170279441Abstract: A clock correction device performs skew adjustment and duty correction of an input clock concurrently or in parallel. The clock correction device includes a correction circuit that performs skew adjustment of an input clock by analog control using a skew adjustment signal based on a phase difference between an output clock and a reference clock, receives a duty control signal, and performs duty correction of the input clock by digital control, a skew detection circuit that receives inputs of the output clock and the reference clock and, when only the reference clock is in a predetermined state, outputs a detection signal that changes to the predetermined state, an integration circuit that integrates the detection signal and generates a first voltage signal, and a comparator that compares the first voltage signal and a first reference signal to thereby generate the skew adjustment signal.Type: ApplicationFiled: March 22, 2017Publication date: September 28, 2017Applicant: MegaChips CorporationInventor: Shingo Adachi
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Patent number: 9692401Abstract: A skew adjustment circuit comprises a phase adjustment circuit that adjusts a phase of a first input clock based on a predetermined phase control signal, and outputs it as an output clock, a logical circuit that performs a logical operation between signals that are input, an integral circuit that generates a predetermined voltage signal, based on a result of the logical operation by the logical circuit, a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal, a first controller that generates the predetermined phase control signal based on a result of the comparison by the comparator, and a second controller that performs control for selecting a signal that is to be input to the logical circuit. The second controller, in a first mode, performs the control such that the output clock and a second input clock are selected.Type: GrantFiled: November 10, 2015Date of Patent: June 27, 2017Assignee: MegaChips CorporationInventor: Shingo Adachi
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Publication number: 20160134267Abstract: A skew adjustment circuit comprises a phase adjustment circuit that adjusts a phase of a first input clock based on a predetermined phase control signal, and outputs it as an output clock, a logical circuit that performs a logical operation between signals that are input, an integral circuit that generates a predetermined voltage signal, based on a result of the logical operation by the logical circuit, a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal, a first controller that generates the predetermined phase control signal based on a result of the comparison by the comparator, and a second controller that performs control for selecting a signal that is to be input to the logical circuit. The second controller, in a first mode, performs the control such that the output clock and a second input clock are selected.Type: ApplicationFiled: November 10, 2015Publication date: May 12, 2016Applicant: MegaChips CorporationInventor: Shingo Adachi