Abstract: A semiconductor integrated circuit includes "n" cascaded inverters IV.sub.j ("j"="1" to "n") formed of MOS transistors. The size of an input side MOS transistor and the size of an output side MOS transistor of each inverter are determined so that an input capacitance CG.sub.j and an output load capacitance CL.sub.j of each inverter satisfy the following relationships: F.sub.j =(CG.sub.(j+1) +CL.sub.j)/CG.sub.j and F.sub.(j+1) =F.sub.j -(CL.sub.j /CG.sub.j).

Abstract: In a constant-voltage generating circuit wherein a first series circuit of PMOS transistors, a second series circuit of a PMOS transistor and an NMOS transistor and a third series circuit of PMOS transistors are connected between a power source line and a ground line, a capacitive element is connected between a common node of the PMOS transistors of the first series circuit and the ground line. In addition to this capacitive element, another capacitive element may be connected between the node and the power source line. Since the node is connected to gates of one of the PMOS transistors of the first series circuit and the PMOS transistor of the second series circuit, the capacitance at this node with respect to the power source line is large. Thus, when the power supply voltage fluctuates abruptly, the voltage at the first node also changes and thus the output voltage also changes.

Abstract: A memory circuit having an improved address change detect circuit which, upon a change of address, forms a first internal one-shot signal for resetting the memory circuit and a second internal one-shot signal for enabling the memory circuit is disclosed. The memory circuit further has a function which, after the read-out data is held by the latch circuit, stops the addressing operation in synchronism with the termination of the second internal one-shot signal, wherein the period for transitting the sense amplifier output to the latch circuit is determined by a period for generating the second internal one-shot signal and, when the first internal one-shot signal is generated, the transmission is preferentially inhibited irrespective of the second internal one-shot signal.