Abstract: A microcontroller includes a CPU (Central Processing Unit), a data input unit, and an oscillator that supplies a clock signal in response to operational modes of the microcontroller. The operational modes include a STOP mode, a SNOOZE mode and a RUN mode, in the STOP mode, the oscillator and the CPU are stopped, in the RUN mode, the CPU and the data input unit operate using the clock signal supplied from the oscillator, and in the SNOOZE mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives first data, and the microcontroller switches to the RUN mode after the data input unit receives second data using the clock signal.

Abstract: A microcontroller includes a CPU (Central Processing Unit), a data input unit, and an oscillator that supplies a clock signal in response to operational modes of the microcontroller. The operational modes include a STOP mode, a SNOOZE mode and a RUN mode, in the STOP mode, the oscillator and the CPU are stopped, in the RUN mode, the CPU and the data input unit operate using the clock signal supplied from the oscillator, and in the SNOOZE mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives first data, and the microcontroller switches to the RUN mode after the data input unit receives second data using the clock signal.

Abstract: A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated.

Abstract: A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated.

Abstract: An A/D (analog-to-digital) conversion circuit includes an input signal selecting circuit configured to output voltage signals of different signal levels in response to control signals in an adjustment mode before A/D conversion of an analog signal in a practical mode; an A/D converter configured to perform A/D conversion on the voltage signals in response to an adjustment sampling clock signal in the adjustment mode to output adjustment conversion values; and a sampling timing adjusting circuit configured to delay a reference sampling clock signal based on a delay value selected in response to a selection signal in the adjustment mode to output the adjustment sampling clock signal to the A/D converter.

Abstract: An A/D (analog-to-digital) conversion circuit includes an input signal selecting circuit configured to output voltage signals of different signal levels in response to control signals in an adjustment mode before A/D conversion of an analog signal in a practical mode; an A/D converter configured to perform A/D conversion on the voltage signals in response to an adjustment sampling clock signal in the adjustment mode to output adjustment conversion values; and a sampling timing adjusting circuit configured to delay a reference sampling clock signal based on a delay value selected in response to a selection signal in the adjustment mode to output the adjustment sampling clock signal to the A/D converter.