Abstract: There is provided a programmable logic array in which a precharge circuit is provided separately from precharge transistors. The precharge circuit can connect the one of wirings connecting memory cell transistors out of the memory cell transistor group constituting an AND plane to a power supply voltage at a same timing as that of the precharge transistors. Accordingly, the programmable logic array having the AND plane which can prevent variation of an output by improving charge share tolerance can be provided.

Abstract: A precharge transistor precharges a bus. A discharge transistor discharges the bus. A push-pull driver is connected to the bus, and consists of a p-channel MOS transistor and an n-channel MOS transistor. The push-pull driver sets the potential of the bus to "H" level or "L" level. A detection circuit detects which one of the discharge transistor and the push-pull driver is being driven. When the push-pull drive is being driven, a control circuit renders the precharge transistor inoperative.

Abstract: A bit position encoder comprises a plurality of judging circuits corresponding in number to bits of input data and connected to receive respective bits of the input data in parallel and a signal specifying the processing sequence for making a judgment on the basis of the result of a judgment from an adjacent judging circuit that has made a judgment of whether a corresponding input bit input thereto has a predetermined value and supplying the result of the judgment to an adjacent judging circuit that has not performed judgment processing yet, a circuit responsive to the results of judgments from the judging circuits for pointing out the bit position in the predetermined value appears first in the direction of judgment processing sequence in a binary code, and a circuit connected to receive the input bits for supplying a result of the logical OR of the input bits to the judging circuits.