Abstract: A switching regulator control circuit, having: a slope circuit 3 for generating a slope voltage VSLP on the basis of a clock signal CLK of a prescribed frequency; an error amplifier 1 for generating an error signal Vc corresponding to the difference between a reference voltage VREF and a voltage VFB corresponding to the output voltage of a switching regulator; a comparator 4 for comparing the error signal Vc and the slope voltage VSLP; and an RS flip-flop 6 set on the basis of the clock signal CLK and reset by a signal outputted by the comparator 4. The timing at which the RS flip-flop 6 is set is delayed with respect to the timing at which the sloping of the slope voltage VSLP is started.

Abstract: A printed circuit board has: a first wiring pattern laid in a first layer such that, when a predetermined component is mounted in a predetermined mounting region, a first current path in an open ring shape leading from a first end to a second end is formed; a second wiring pattern laid in a second layer different from the first layer such that a second current path in an open ring shape leading from a third end to a fourth end is formed; a first conductive member formed between the second and third ends; and a second conductive member formed between the first and fourth ends. The first and second wiring patterns are so laid that, as seen in their respective plan views, the directions of the currents flowing across the first and second current paths, respectively, are opposite to each other.

Abstract: A printed circuit board has: a first wiring pattern laid in a first layer such that, when a predetermined component is mounted in a predetermined mounting region, a first current path in an open ring shape leading from a first end to a second end is formed; a second wiring pattern laid in a second layer different from the first layer such that a second current path in an open ring shape leading from a third end to a fourth end is formed; a first conductive member formed between the second and third ends; and a second conductive member formed between the first and fourth ends. The first and second wiring patterns are so laid that, as seen in their respective plan views, the directions of the currents flowing across the first and second current paths, respectively, are opposite to each other.

Abstract: A printed circuit board has: a first wiring pattern laid in a first layer such that, when a predetermined component is mounted in a predetermined mounting region, a first current path in an open ring shape leading from a first end to a second end is formed; a second wiring pattern laid in a second layer different from the first layer such that a second current path in an open ring shape leading from a third end to a fourth end is formed; a first conductive member formed between the second and third ends; and a second conductive member formed between the first and fourth ends. The first and second wiring patterns are so laid that, as seen in their respective plan views, the directions of the currents flowing across the first and second current paths, respectively, are opposite to each other.

Abstract: A switching regulator control circuit, having: a slope circuit 3 for generating a slope voltage VSLP on the basis of a clock signal CLK of a prescribed frequency; an error amplifier 1 for generating an error signal Vc corresponding to the difference between a reference voltage VREF and a voltage VFB corresponding to the output voltage of a switching regulator; a comparator 4 for comparing the error signal Vc and the slope voltage VSLP; and an RS flip-flop 6 set on the basis of the clock signal CLK and reset by a signal outputted by the comparator 4. The timing at which the RS flip-flop 6 is set is delayed with respect to the timing at which the sloping of the slope voltage VSLP is started.

Abstract: There is provided a linear regulator including: a first output transistor connected between a first input terminal to which a first input voltage is applied and an output terminal from which an output voltage is outputted; a second output transistor connected between a second input terminal to which a second input voltage is applied and the output terminal; and a control circuit configured to control the first output transistor when the second input voltage of a predetermined range is not supplied to the second input terminal, and to control the second output transistor when the first input voltage of the predetermined range is not supplied to the first input terminal.

Abstract: In a switching regulator, a first switch and a second switch are turned ON and OFF complementarily according to an output voltage. In a step-up/down mode, a third switch and a fourth switch are turned ON and OFF complementarily while the ON-duty D of the third switch is kept fixed.

Abstract: Provided is an integrated circuit package which complementarily switches on/off a MOS transistor Q1 (first switch) and MOS transistor Q2 (second switch) in accordance with an output voltage Vout, and which externally outputs a pulse signal having a fixed on-duty D during a step-up/step-down mode. The integrated circuit package has a determination unit 61 for determining the impedance of an external component connected to an external pin P5 that outputs the pulse signal to the exterior during the step-up/step-down mode, and determining whether the external component is a third switch on the basis of the impedance determination result.

Abstract: A phase compensation circuit, being for compensating phase of a first voltage inputted to a PWM comparator of a DC/DC converter having a sleep mode, includes: a phase compensation resistor part including a resistor; a phase compensation capacitor part including a plurality of capacitors; and a switch group arranged to change over the capacitors, in the sleep mode, to a first connection state in which at least one of the capacitors is charged with a first bias voltage and to change over the capacitors, at cancellation of the sleep mode, to a second connection state in which the first voltage is set to a desired initial value.

Abstract: A printed circuit board has: a first wiring pattern laid in a first layer such that, when a predetermined component is mounted in a predetermined mounting region, a first current path in an open ring shape leading from a first end to a second end is formed; a second wiring pattern laid in a second layer different from the first layer such that a second current path in an open ring shape leading from a third end to a fourth end is formed; a first conductive member formed between the second and third ends; and a second conductive member formed between the first and fourth ends. The first and second wiring patterns are so laid that, as seen in their respective plan views, the directions of the currents flowing across the first and second current paths, respectively, are opposite to each other.

Abstract: A phase compensation circuit, being for compensating phase of a first voltage inputted to a PWM comparator of a DC/DC converter having a sleep mode, includes: a phase compensation resistor part including a resistor; a phase compensation capacitor part including a plurality of capacitors; and a switch group arranged to change over the capacitors, in the sleep mode, to a first connection state in which at least one of the capacitors is charged with a first bias voltage and to change over the capacitors, at cancellation of the sleep mode, to a second connection state in which the first voltage is set to a desired initial value.

Abstract: In a switching regulator, a first switch and a second switch are turned ON and OFF complementarily according to an output voltage. In a step-up/down mode, a third switch and a fourth switch are turned ON and OFF complementarily while the ON-duty D of the third switch is kept fixed.

Abstract: The switching regulator according to the present invention comprises an oscillation circuit for generating a clock signal having a predetermined oscillation frequency; and a switching signal generation circuit for generating a switching signal for driving a switching element connected to an output circuit; wherein the switching signal generation circuit varies the ON time of the switching signal so that the frequency of the switching signal approaches the frequency of the clock signal; and varies the timing at which the switching signal is ON so that an output voltage outputted from the output circuit approaches a predetermined reference voltage.