Abstract: A reed valve 1 includes: a valve body 4; a valve seat 6 having a valve hole 3 for passage of a fluid J; a casing 8 accommodating the valve body 4; and a reed 10 including an arm part 18 having a first end portion 22 connected to the casing 8, and a valve body support part 20 connected to a second end portion 24 of the arm part 18 and supporting the valve body 4 so that the valve hole 3 can be opened and closed. When a first direction D1 is a flow direction of the fluid J in the valve hole 3, and a first surface 21 is a surface facing downstream in the first direction D1 among an inner surface of the casing 8, the first surface 21 includes a recess 27 facing the arm part 18.

Abstract: A reed valve 1 includes: a valve body 4; a valve seat 6 having a valve hole 3 for passage of a fluid J; a casing 8 accommodating the valve body 4; and a reed 10 including an arm part 18 having a first end portion 22 connected to the casing 8, and a valve body support part 20 connected to a second end portion 24 of the arm part 18 and supporting the valve body 4 so that the valve hole 3 can be opened and closed. When a first direction D1 is a flow direction of the fluid J in the valve hole 3, and a first surface 21 is a surface facing downstream in the first direction D1 among an inner surface of the casing 8, the first surface 21 includes a recess 27 facing the arm part 18.

Abstract: A base station apparatus, communication terminal apparatus, communication system, and communication method are provided that enable the data part transmission amount to be increased, that are resistant to frequency selective fading, and that enable a BS with low transmission loss to be selected.

Abstract: A correlation calculator and carrier frequency synchronization detection circuit are provided that enable a code phase, carrier frequency, and carrier frequency phase match to be detected even if a carrier frequency is greatly displaced. A correlation value calculation section (130) has n storage elements (501 through 507) that store a spread code, n-integral-multiple first delay elements (401 through 414) that perform sequential shifting by delaying an I component baseband signal by a fixed time interval, and n-integral-multiple first multipliers (701 through 714) that respectively perform multiplication between sequentially shifted I component baseband signals and the storage elements (501 through 507). The same kind of configuration as in the case of an above I component baseband signal is also provided for a Q component baseband signal.

Abstract: A base station apparatus, communication terminal apparatus, communication system, and communication method are provided that enable the data part transmission amount to be increased, that are resistant to frequency selective fading, and that enable a BS with low transmission loss to be selected.

Abstract: Output terminal 340 extracts specific subcarrier data assigned by a base station from at least one of a plurality of butterfly operation sections provided in output terminal 340. The butterfly operation sections in first node 320, second node 330, and output terminal 340 make only butterfly operation sections relating to extraction of the specific subcarrier data perform the butterfly operation. Thereby, unnecessary butterfly operation performed in butterfly operation unit 300 is omitted.

Abstract: A code generator capable of performing the shift operation at high speed on a small circuit scale by providing combination circuits (matrix operation weights) in response to the shift count. The code generator has a register 10, a selection circuit 11, combination circuits 12 to 16 for performing matrix operation, and a control circuit 17 for controlling the timing of storing data in the selection circuit 11 and the register 10. One of the combination circuits 12 to 16 is selected in response to a select signal S from the control circuit 17 and data is output from the register 10 in response to a register storage clock Rck.

Abstract: A sync pattern detecting circuit detects a sync pattern from the input data to output a sync pattern detecting signal. A frame counter counts clock signals for the bit number of one frame to output a frame count signal. A sync manage circuit sets a window time area therein, and outputs a sync signal when the sync pattern detecting signal is input in the window time area. The width of the window time area is variable. The width of the window time area is controlled at timings at which the sync pattern detecting signal and the frame count signal are input.

Abstract: A serial/parallel converter has a function of forwarding data of remainder bits of p in number (e.g., 3) less than the serial/parallel number, which are positioned at the end of serial data, from the head from latches to p parallel output terminals via selectors. Accordingly, parallel data in which the data of remainder bit number are arranged correctly can be serially developed even though a simple delay amount is an arbitrary bit width. Thus, contemplated is a line memory of simple delay type which can set the simple delay amount to an arbitrary bit width, while performing serial/parallel conversion.