Patents by Inventor Shingo Karino

Shingo Karino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8019008
    Abstract: A base station apparatus, communication terminal apparatus, communication system, and communication method are provided that enable the data part transmission amount to be increased, that are resistant to frequency selective fading, and that enable a BS with low transmission loss to be selected.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: September 13, 2011
    Assignee: Panasonic Corporation
    Inventor: Shingo Karino
  • Publication number: 20110032974
    Abstract: A correlation calculator and carrier frequency synchronization detection circuit are provided that enable a code phase, carrier frequency, and carrier frequency phase match to be detected even if a carrier frequency is greatly displaced. A correlation value calculation section (130) has n storage elements (501 through 507) that store a spread code, n-integral-multiple first delay elements (401 through 414) that perform sequential shifting by delaying an I component baseband signal by a fixed time interval, and n-integral-multiple first multipliers (701 through 714) that respectively perform multiplication between sequentially shifted I component baseband signals and the storage elements (501 through 507). The same kind of configuration as in the case of an above I component baseband signal is also provided for a Q component baseband signal.
    Type: Application
    Filed: October 13, 2010
    Publication date: February 10, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Shingo Karino
  • Publication number: 20080170633
    Abstract: A base station apparatus, communication terminal apparatus, communication system, and communication method are provided that enable the data part transmission amount to be increased, that are resistant to frequency selective fading, and that enable a BS with low transmission loss to be selected.
    Type: Application
    Filed: January 3, 2008
    Publication date: July 17, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Shingo KARINO
  • Publication number: 20070198623
    Abstract: Output terminal 340 extracts specific subcarrier data assigned by a base station from at least one of a plurality of butterfly operation sections provided in output terminal 340. The butterfly operation sections in first node 320, second node 330, and output terminal 340 make only butterfly operation sections relating to extraction of the specific subcarrier data perform the butterfly operation. Thereby, unnecessary butterfly operation performed in butterfly operation unit 300 is omitted.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 23, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Shingo KARINO
  • Patent number: 6738413
    Abstract: A code generator capable of performing the shift operation at high speed on a small circuit scale by providing combination circuits (matrix operation weights) in response to the shift count. The code generator has a register 10, a selection circuit 11, combination circuits 12 to 16 for performing matrix operation, and a control circuit 17 for controlling the timing of storing data in the selection circuit 11 and the register 10. One of the combination circuits 12 to 16 is selected in response to a select signal S from the control circuit 17 and data is output from the register 10 in response to a register storage clock Rck.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: May 18, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shingo Karino
  • Patent number: 5677935
    Abstract: A sync pattern detecting circuit detects a sync pattern from the input data to output a sync pattern detecting signal. A frame counter counts clock signals for the bit number of one frame to output a frame count signal. A sync manage circuit sets a window time area therein, and outputs a sync signal when the sync pattern detecting signal is input in the window time area. The width of the window time area is variable. The width of the window time area is controlled at timings at which the sync pattern detecting signal and the frame count signal are input.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: October 14, 1997
    Assignee: Matsuhita Electric Industrial Co., Ltd.
    Inventor: Shingo Karino
  • Patent number: 5508967
    Abstract: A serial/parallel converter has a function of forwarding data of remainder bits of p in number (e.g., 3) less than the serial/parallel number, which are positioned at the end of serial data, from the head from latches to p parallel output terminals via selectors. Accordingly, parallel data in which the data of remainder bit number are arranged correctly can be serially developed even though a simple delay amount is an arbitrary bit width. Thus, contemplated is a line memory of simple delay type which can set the simple delay amount to an arbitrary bit width, while performing serial/parallel conversion.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: April 16, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shingo Karino