Patents by Inventor Shingo Komatsu

Shingo Komatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8871567
    Abstract: The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)?C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 28, 2014
    Assignees: Panasonic Corporation, Dai-Ichi Kogyo Seiyaku Co., Ltd.
    Inventors: Koichi Hirano, Shingo Komatsu, Yasuteru Saito, Naoki Ike
  • Patent number: 8709293
    Abstract: There is provided a flip-chip mounting resin composition which can be used for a flip-chip mounting process that is high in productivity and reliability and thus can be applicable to a flip-chip mounting of a next-generation LSI. This flip-chip mounting resin composition comprises a resin, metal particles and a convection additive 12 that boils upon heating the resin 13. Upon the heating of the resin 13, the metal particles melt and the boiling convection additive 12 convects within the resin 13. This flip-chip mounting resin composition is supplied between a circuit substrate 10 and a semiconductor chip 20, and subsequently the resin 13 is heated so that the molten metal particles self-assemble into the region between each electrode of the circuit substrate and each electrode of the semiconductor chip. As a result, an electrical connection is formed between each electrode of the circuit substrate and each electrode of the semiconductor chip.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: April 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Takashi Kitae, Seiji Karashima, Koichi Hirano, Toshiyuki Kojima, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita
  • Patent number: 8617943
    Abstract: A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: December 31, 2013
    Assignee: Panasonic Corporation
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano, Yoshihisa Yamashita, Shingo Komatsu
  • Publication number: 20130032797
    Abstract: The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)?C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0.
    Type: Application
    Filed: December 19, 2011
    Publication date: February 7, 2013
    Inventors: Koichi Hirano, Shingo Komatsu, Yasuteru Saito, Naoki Ike
  • Patent number: 8344264
    Abstract: A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Yutaka Kumano, Hideki Iwaki, Tetsuyoshi Ogura, Shingo Komatsu, Koichi Hirano
  • Patent number: 8039307
    Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 18, 2011
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Kojima, Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Shingo Komatsu
  • Patent number: 7977741
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: July 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Patent number: 7921551
    Abstract: An electronic component mounting method includes a step of applying a resin composition (3) including solder powder, convective additive and resin having fluidity at the melting temperature of the solder powder on a main surface of a wiring substrate (1) provided with conductive wirings and connecting terminals, a step of preparing a group of electronic components consisting of a plurality of electronic components (7, 8 and 9) including at least a passive component, the respective electronic components comprising electrode terminals, position-aligning connecting terminals with the electrode terminals, and making the group of electronic components abut a surface of the resin composition, a step of heating at least the resin composition so as to melt solder powder and make the solder powder self-assembled between the connecting terminals and the electrode terminals by the convective additive, and thereby connecting the connecting terminals and the electrode terminals by soldering, and a step of fixedly adhering
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: April 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshihisa Yamashita, Seiji Karashima, Takashi Kitae, Seiichi Nakatani, Toshiyuki Kojima, Shingo Komatsu
  • Patent number: 7911064
    Abstract: A mounted body of the present invention includes: a multilayer semiconductor chip 20 including a plurality of semiconductor chips 10 (10a, 10b) that are stacked; and a mounting board 13 on which the multilayer semiconductor chip 20 is mounted. In this mounted body, each of the semiconductor chips 10 (10a, 10b) in the multilayer semiconductor chip 20 has a plurality of element electrodes 12 (12a, 12b) on a chip surface 21 (21a, 21b) facing toward the mounting board 13. On the mounting board 13, electrode terminals 14 are formed so as to correspond to the plurality of element electrodes (12a, 12b), respectively, and the electrode terminals 14 of the mounting board and the element electrodes (12a, 12b) are connected electrically to each other via solder bump formed as a result of assembly of solder particles. With this configuration, a mounted body on which a stacked package is mounted can be manufactured easily.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Shingo Komatsu, Seiichi Nakatani, Seiji Karashima, Toshiyuki Kojima, Takashi Kitae, Yoshihisa Yamashita
  • Publication number: 20110049598
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Application
    Filed: November 4, 2010
    Publication date: March 3, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Koichi HIRANO, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Patent number: 7888789
    Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: February 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
  • Patent number: 7851281
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Koichi Hirano, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Publication number: 20100276691
    Abstract: A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.
    Type: Application
    Filed: July 22, 2009
    Publication date: November 4, 2010
    Inventors: Takashi Ichiryu, Seiichi Nakatani, Koichi Hirano, Yoshihisa Yamashita, Shingo Komatsu
  • Publication number: 20100224986
    Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 9, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Toshiyuki Kojima, Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Shingo Komatsu
  • Patent number: 7713787
    Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: May 11, 2010
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Kojima, Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Shingo Komatsu
  • Publication number: 20100012936
    Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.
    Type: Application
    Filed: October 1, 2008
    Publication date: January 21, 2010
    Inventors: Koichi Hirano, Seiichi Nakatani, Shingo Komatsu, Yoshihisa Yamashita, Takashi Ichiryu
  • Publication number: 20090321124
    Abstract: A pair of discretionary points on a principal surface of a block are coupled to each other with a metal wire having a length larger than a distance between the pair of discretionary points, liquid resin is applied to the principal surface so as to cover the metal wire and then cured, so that a resin-cured material is formed, and the upper-surface portion of the resin-cured material is removed together with an intermediate portion of the metal wire, and then the block is removed from the resin-cured material.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 31, 2009
    Inventors: Yutaka KUMANO, Hideki IWAKI, Tetsuyoshi OGURA, Shingo KOMATSU, Koichi HIRANO
  • Patent number: 7611040
    Abstract: A method for forming solder bumps for realizing high density mounting and a highly reliable method for mounting a semiconductor device is provided. A flat plate having a plurality of projections or recesses thereon is prepared; the flat plate is aligned to oppose an electronic component and a resin composition including a solder powder is supplied to a gap between the flat plate and the electronic component; the resin composition is annealed to melt the solder powder included in the resin composition for growing the solder powder up to the level of the surface of the flat plate by allowing the melted solder powder to self-assemble on terminals, so as to form solder bumps on the terminals; and the flat plate is removed after cooling and solidifying the solder bumps. Thus, the solder bumps having pits corresponding to the projections or having protrusions corresponding to the recesses are formed.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: November 3, 2009
    Assignee: Panasonic Corporation
    Inventors: Takashi Kitae, Seiichi Nakatani, Toshiyuki Kojima, Shingo Komatsu, Yoshihisa Yamashita
  • Publication number: 20090230546
    Abstract: A mounted body of the present invention includes: a multilayer semiconductor chip 20 including a plurality of semiconductor chips 10 (10a, 10b) that are stacked; and a mounting board 13 on which the multilayer semiconductor chip 20 is mounted. In this mounted body, each of the semiconductor chips 10 (10a, 10b) in the multilayer semiconductor chip 20 has a plurality of element electrodes 12 (12a, 12b) on a chip surface 21 (21a, 21b) facing toward the mounting board 13. On the mounting board 13, electrode terminals 14 are formed so as to correspond to the plurality of element electrodes (12a, 12b), respectively, and the electrode terminals 14 of the mounting board and the element electrodes (12a, 12b) are connected electrically to each other via solder bump formed as a result of assembly of solder particles. With this configuration, a mounted body on which a stacked package is mounted can be manufactured easily.
    Type: Application
    Filed: February 28, 2006
    Publication date: September 17, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
    Inventors: Shingo Komatsu, Seiichi Nakatani, Seiji Karashima, Toshiyuki Kojima, Takashi Kitae, Yoshihisa Yamashita
  • Publication number: 20090223705
    Abstract: An electronic component mounting method includes a step of applying a resin composition (3) including solder powder, convective additive and resin having fluidity at the melting temperature of the solder powder on a main surface of a wiring substrate (1) provided with conductive wirings and connecting terminals, a step of preparing a group of electronic components consisting of a plurality of electronic components (7, 8 and 9) including at least a passive component, the respective electronic components comprising electrode terminals, position-aligning connecting terminals with the electrode terminals, and making the group of electronic components abut a surface of the resin composition, a step of heating at least the resin composition so as to melt solder powder and make the solder powder self-assembled between the connecting terminals and the electrode terminals by the convective additive, and thereby connecting the connecting terminals and the electrode terminals by soldering, and a step of fixedly adhering
    Type: Application
    Filed: March 23, 2006
    Publication date: September 10, 2009
    Inventors: Yoshihisa Yamashita, Seiji Karashima, Takashi Kitae, Seiichi Nakatani, Toshiyuki Kojima, Shingo Komatsu