Abstract: An envelope processing apparatus conveys an envelope to an enclosing position and encloses an enclosure on which specific information is formed at a formation position. The enclosing device includes: an envelope conveyor to convey the enclosure to the enclosing position to insert the enclosure into the envelope; a sensor to acquire, as an image, a structure of the envelope during conveyance, and acquire transparent-portion information indicating a position of a transparent portion in the envelope; an envelope holder to hold the envelope in a state in which the enclosure is insertable; and control circuitry to output position adjustment information for adjusting a position of the envelope in a width direction of the envelope at the enclosing position or a position of the specific information in a conveyance direction of the envelope, based on relative positions between the formation position of the specific information and the position of the transparent portion.

Abstract: An enclosing-sealing apparatus includes a flap opener that opens a flap of an envelope while the envelope is conveyed to an enclosing position. A first envelope detector is disposed upstream from the flap opener in an envelope conveyance direction and detects both ends of the envelope in the envelope conveyance direction. A second envelope detector is disposed downstream from the flap opener in the envelope conveyance direction and detects both ends of the envelope in the envelope conveyance direction in an open state in which the flap opens. A controller determines the open state of the flap based on a first detection result sent from the first envelope detector and a second detection result sent from the second envelope detector. The controller performs troubleshooting for enclosing the enclosure into the envelope if the controller determines that the open state of the flap is faulty.

Abstract: A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Abstract: A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Abstract: A processing device includes: a first processor configured to execute a determination process; and a second processor configured to communicate with the first processor via an internal bus, wherein the determination process includes processes of determining that the abnormality occurs inside the processing device when first reference data transmitted to the second processor and first diagnostic data that is response data to the first reference data do not correspond to each other, and determining that the abnormality occurs in at least one of an external bus or an external device when the first reference data and the first diagnostic data correspond to each other and second reference data transmitted to the external device and second diagnostic data that is response data to the second reference data do not correspond to each other.

Abstract: A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Abstract: A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Abstract: A processing device includes: a first processor configured to execute a determination process; and a second processor configured to communicate with the first processor via an internal bus, wherein the determination process includes processes of determining that the abnormality occurs inside the processing device when first reference data transmitted to the second processor and first diagnostic data that is response data to the first reference data do not correspond to each other, and determining that the abnormality occurs in at least one of an external bus or an external device when the first reference data and the first diagnostic data correspond to each other and second reference data transmitted to the external device and second diagnostic data that is response data to the second reference data do not correspond to each other.

Abstract: A high-frequency amplifier includes: a carrier amplifier which amplifies a first signal; a peak amplifier which amplifies a second signal; a first matching circuit which is connected to the output terminal of the carrier amplifier; a second matching circuit which is connected to the output terminal of the peak amplifier; a first transmission line which is connected between the first matching circuit and the second matching circuit, and has an electric length that is less than ¼ of the wavelength of the center frequency of a predetermined frequency band. The phase rotation by a series inductor which is included in each of the first matching circuit and the second matching circuit and has one end that has been grounded is opposite to the phase rotation by the first transmission line.

Abstract: An abnormality detection system configured to detect abnormal communication includes a first electronic control unit, a plurality of second electronic control units, a plurality of connector connection portions, and a processor. The connector connection portions are provided on a communication path between the first electronic control unit and the second electronic control units. Each connector connection portion includes a first connector portion and a second connector portion. The processor is configured to determine that, when abnormal communication occurs, one of the connector connection portions that is experiencing abnormal communication with all the second electronic control units connected to the second connector portion and that includes the second connector portion connected to the largest number of second electronic control units is abnormal.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A high-frequency amplifier includes: a carrier amplifier amplifying a first signal; a peak amplifier amplifying a second signal; a first transmission line connected between output terminals of the carrier amplifier and the peak amplifier, and having an electrical length equal to one-quarter wavelength of a center frequency in the predetermined frequency band; a second transmission line connected between one end of the first transmission line and the output terminal of the high-frequency amplifier, and having an electrical length equal to one-quarter wavelength of the center frequency; and an impedance compensation circuit with one end connected to a node between the first transmission line and the second transmission line. At the center frequency, an imaginary part of an impedance during viewing of the impedance compensation circuit from the node is opposite in polarity from an imaginary part of an impedance during viewing of the second transmission line from the node.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A high-frequency amplifier includes: a carrier amplifier amplifying a first signal; a peak amplifier amplifying a second signal; a first transmission line connected between output terminals of the carrier amplifier and the peak amplifier, and having an electrical length equal to one-quarter wavelength of a center frequency in the predetermined frequency band; a second transmission line connected between one end of the first transmission line and the output terminal of the high-frequency amplifier, and having an electrical length equal to one-quarter wavelength of the center frequency; and an impedance compensation circuit with one end connected to a node between the first transmission line and the second transmission line. At the center frequency, an imaginary part of an impedance during viewing of the impedance compensation circuit from the node is opposite in polarity from an imaginary part of an impedance during viewing of the second transmission line from the node.

Abstract: A controller according to the present disclosure includes a target current controller, a dither controlling unit, an output-duty generating unit, and a Pulse-Width-Modulation-pulse (PWM-pulse) converting unit. The dither controlling unit generates a dither duty for providing, to a target current duty of a load, a dither having predetermined dither period. The target current controller calculates, for each predetermined feedback period, an average value of a feedback current from the load and generates the target current duty based on the average value. The output-duty generating unit generates an output duty obtained by adding the dither duty generated by the dither controlling unit to the target current duty generated by the target current controller. The PWM-pulse converting unit converts the output duty generated by the output-duty generating unit to PWM pulses.

Abstract: A controller according to the present disclosure includes a target current controller, a dither controlling unit, an output-duty generating unit, and a Pulse-Width-Modulation-pulse (PWM-pulse) converting unit. The dither controlling unit generates a dither duty for providing, to a target current duty of a load, a dither having predetermined dither period. The target current controller calculates, for each predetermined feedback period, an average value of a feedback current from the load and generates the target current duty based on the average value. The output-duty generating unit generates an output duty obtained by adding the dither duty generated by the dither controlling unit to the target current duty generated by the target current controller. The PWM-pulse converting unit converts the output duty generated by the output-duty generating unit to PWM pulses.

Abstract: A semiconductor device includes a source electrode portion and a drain electrode formed on a semiconductor stacked body so as to be at an interval from each other, and a gate electrode formed between the source electrode portion and the drain electrode at an interval from the source electrode portion and the drain electrode. The source electrode portion includes a first recess electrode being directly in contact with a two-dimensional electron gas layer formed in the first nitride semiconductor layer, and a surface electrode formed between the gate electrode and the first recess electrode and connected conductively to the two-dimensional electron gas layer. A source potential is applied to the surface electrode and the recess electrode, and a width of the surface electrode in a gate-source direction is 0.4 times or more a distance between a gate-side end of the surface electrode and a source-side end of the gate electrode.

Abstract: A semiconductor device includes a source electrode portion and a drain electrode formed on a semiconductor stacked body so as to be at an interval from each other, and a gate electrode formed between the source electrode portion and the drain electrode at an interval from the source electrode portion and the drain electrode. The source electrode portion includes a first recess electrode being directly in contact with a two-dimensional electron gas layer formed in the first nitride semiconductor layer, and a surface electrode formed between the gate electrode and the first recess electrode and connected conductively to the two-dimensional electron gas layer. A source potential is applied to the surface electrode and the recess electrode, and a width of the surface electrode in a gate-source direction is 0.4 times or more a distance between a gate-side end of the surface electrode and a source-side end of the gate electrode.