Patents by Inventor Shingo Matsuda

Shingo Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10156296
    Abstract: A controller according to the present disclosure includes a target current controller, a dither controlling unit, an output-duty generating unit, and a Pulse-Width-Modulation-pulse (PWM-pulse) converting unit. The dither controlling unit generates a dither duty for providing, to a target current duty of a load, a dither having predetermined dither period. The target current controller calculates, for each predetermined feedback period, an average value of a feedback current from the load and generates the target current duty based on the average value. The output-duty generating unit generates an output duty obtained by adding the dither duty generated by the dither controlling unit to the target current duty generated by the target current controller. The PWM-pulse converting unit converts the output duty generated by the output-duty generating unit to PWM pulses.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: December 18, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Tomohito Kato, Takeshi Dowa, Shingo Matsuda, Tomoyuki Kato
  • Publication number: 20180142800
    Abstract: A controller according to the present disclosure includes a target current controller, a dither controlling unit, an output-duty generating unit, and a Pulse-Width-Modulation-pulse (PWM-pulse) converting unit. The dither controlling unit generates a dither duty for providing, to a target current duty of a load, a dither having predetermined dither period. The target current controller calculates, for each predetermined feedback period, an average value of a feedback current from the load and generates the target current duty based on the average value. The output-duty generating unit generates an output duty obtained by adding the dither duty generated by the dither controlling unit to the target current duty generated by the target current controller. The PWM-pulse converting unit converts the output duty generated by the output-duty generating unit to PWM pulses.
    Type: Application
    Filed: October 13, 2017
    Publication date: May 24, 2018
    Applicant: FUJITSU TEN LIMITED
    Inventors: Tomohito KATO, Takeshi DOWA, Shingo MATSUDA, Tomoyuki KATO
  • Patent number: 9425302
    Abstract: A semiconductor device includes a source electrode portion and a drain electrode formed on a semiconductor stacked body so as to be at an interval from each other, and a gate electrode formed between the source electrode portion and the drain electrode at an interval from the source electrode portion and the drain electrode. The source electrode portion includes a first recess electrode being directly in contact with a two-dimensional electron gas layer formed in the first nitride semiconductor layer, and a surface electrode formed between the gate electrode and the first recess electrode and connected conductively to the two-dimensional electron gas layer. A source potential is applied to the surface electrode and the recess electrode, and a width of the surface electrode in a gate-source direction is 0.4 times or more a distance between a gate-side end of the surface electrode and a source-side end of the gate electrode.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: August 23, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Wataru Kanaga, Hiroaki Kawano, Shingo Matsuda, Katsuhiko Kawashima
  • Publication number: 20160133739
    Abstract: A semiconductor device includes a source electrode portion and a drain electrode formed on a semiconductor stacked body so as to be at an interval from each other, and a gate electrode formed between the source electrode portion and the drain electrode at an interval from the source electrode portion and the drain electrode. The source electrode portion includes a first recess electrode being directly in contact with a two-dimensional electron gas layer formed in the first nitride semiconductor layer, and a surface electrode formed between the gate electrode and the first recess electrode and connected conductively to the two-dimensional electron gas layer. A source potential is applied to the surface electrode and the recess electrode, and a width of the surface electrode in a gate-source direction is 0.4 times or more a distance between a gate-side end of the surface electrode and a source-side end of the gate electrode.
    Type: Application
    Filed: January 20, 2016
    Publication date: May 12, 2016
    Inventors: WATARU KANAGA, HIROAKI KAWANO, SHINGO MATSUDA, KATSUHIKO KAWASHIMA
  • Publication number: 20110003566
    Abstract: An RF power amplifier according to the present invention includes: an RF power amplifying element, a first switch provided in a first transmission path for transmitting a first RF signal output from the RF power amplifying element, a second transmission unit which transmits a second RF signal of higher frequency than the first RF signal output from the RF power amplifying element, and a second second-order harmonic trap circuit connected to an output terminal, and the second transmission unit includes a grounded capacitor, a second transmission path, a Band-I matching circuit, a second switch connected in series to the second transmission path, and the second switch connects the second transmission path to the grounded capacitor when the first RF signal is amplified, and connects the second transmission path to the Band-I matching circuit when the second RF signal is amplified.
    Type: Application
    Filed: June 25, 2010
    Publication date: January 6, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Hirokazu MAKIHARA, Kazuki TATEOKA, Masahiko INAMORI, Shingo MATSUDA
  • Patent number: 7834700
    Abstract: A radio frequency signal is input to the bases of transistors via respective capacitors, is amplified, and is output from the collectors of the transistors. The emitter of each transistor is grounded. A bias current input from a bias circuit is supplied to the bases of the transistors via respective resistors both during low-output operation and during high-output operation. The collectors of the transistors are connected via an impedance circuit to a bias voltage input terminal. Therefore, during high-output operation, a direct current offset voltage is generated by the impedance circuit based on a portion of a radio frequency signal output from the collectors, thereby further increasing the bias current.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: November 16, 2010
    Assignee: Panasonic Corporation
    Inventors: Masahiko Inamori, Kazuki Tateoka, Hirokazu Makihara, Shingo Matsuda, Junji Kaido
  • Patent number: 7768354
    Abstract: A bias circuit operable to supply a bias current to a first transistor includes: a second transistor having a collector terminal connected to a first power supply; a first resistance element having one end connected to an emitter terminal of the second transistor and having the other end connected to a base terminal of the first transistor; a second resistance element having one end connected to the emitter terminal of the second transistor and having the other end connected to ground potential; at least one third resistance element provided between a base terminal of the second transistor and a second power supply; and a plurality of temperature compensation circuits connected to the base terminal of the second transistor which are operable to control a base potential of the second transistor so that the potential falls as a temperature rises.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: August 3, 2010
    Assignee: Panasonic Corporation
    Inventors: Shingo Matsuda, Hirokazu Makihara, Kazuki Tateoka, Masahiko Inamori
  • Publication number: 20100151805
    Abstract: In a multi-stage amplifier, a power supply circuit and a multiplier perform control so that, when there are manufacturing variations in, for example, inter-stage capacitance, a collector voltage of a stage immediately preceding a final stage is smaller than a collector voltage of the final stage, thereby suppressing variations in AM-PM characteristics.
    Type: Application
    Filed: August 11, 2009
    Publication date: June 17, 2010
    Inventors: Junji KAIDO, Kazuki Tateoka, Masahiko Inamori, Hirokazu Makihara, Shingo Matsuda
  • Publication number: 20100127781
    Abstract: A radio frequency signal is input to the bases of transistors via respective capacitors, is amplified, and is output from the collectors of the transistors. The emitter of each transistor is grounded. A bias current input from a bias circuit is supplied to the bases of the transistors via respective resistors both during low-output operation and during high-output operation. The collectors of the transistors are connected via an impedance circuit to a bias voltage input terminal. Therefore, during high-output operation, a direct current offset voltage is generated by the impedance circuit based on a portion of a radio frequency signal output from the collectors, thereby further increasing the bias current.
    Type: Application
    Filed: August 4, 2009
    Publication date: May 27, 2010
    Inventors: Masahiko INAMORI, Kazuki TATEOKA, Hirokazu MAKIHARA, Shingo MATSUDA, Junji KAIDO
  • Patent number: 7692491
    Abstract: A radio-frequency power amplifier for preventing a final-stage HBT from being destroyed is provided. To this end, a radio-frequency multistage power amplifier of the present invention includes: a first amplification stage having a first hetero bipolar transistor of which collector output is detected; a second amplification stage which is prior to the first amplification stage and which has a second hetero bipolar transistor in which the detection result is reflected; a first resistor provided between a collector of the second hetero bipolar transistor and a power supply; and a protection circuit which is connected between a collector of the first hetero bipolar transistor and the collector of the second hetero bipolar transistor, detects output from the collector of the first hetero bipolar transistor, and reduces a voltage of the collector of the second hetero bipolar transistor in accordance with the detected output.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: April 6, 2010
    Assignee: Panasonic Corporation
    Inventors: Hirokazu Makihara, Haruhiko Koizumi, Kazuki Tateoka, Masahiko Inamori, Shingo Matsuda
  • Publication number: 20100079211
    Abstract: Provided is a matching circuit, radio-frequency power amplifier, and mobile phone whereby the second harmonic can be suppressed and the loss of fundamental due to the self resonant frequency of components can be reduced. The output matching circuit includes: a transmission line through which a radio-frequency signal is transmitted; and resonators each of which includes a capacitor. The resonators respectively have (i) first terminals connected to substantially a same connecting point on the transmission line and (ii) second terminals that are grounded.
    Type: Application
    Filed: September 22, 2009
    Publication date: April 1, 2010
    Applicant: Panasonic Corporation
    Inventors: Shingo MATSUDA, Kazuki TATEOKA, Masahiko INAMORI, Hirokazu MAKIHARA, Junji KAIDO
  • Publication number: 20100081410
    Abstract: A radio frequency circuit according to the present invention, is a radio frequency circuit for amplifying a radio frequency signal, the radio frequency circuit comprising: an amplifier circuit for amplifying the radio frequency signal and outputting an amplified signal obtained by the amplification of the radio frequency signal; a load circuit connected to an output of the amplifier circuit; a plurality of transmission lines; a selection circuit for selecting a transmission line among the plurality of transmission lines in accordance with a predetermined parameter of the amplified signal so as to connect the selected transmission line to an output of the load circuit; and a conversion circuit for converting, into a predetermined load impedance, a load impedance looking from the amplifier circuit toward an output side of the amplifier circuit, the conversion being performed in the transmission line selected by the selection circuit.
    Type: Application
    Filed: August 5, 2009
    Publication date: April 1, 2010
    Inventors: Junji KAIDO, Masahiko INAMORI, Kazuki TATEOKA, Shingo MATSUDA, Hirokazu MAKIHARA
  • Patent number: 7679438
    Abstract: A small, high performance, multifunctional high frequency circuit that is multiband and multimode compatible reduces loss from a switch formed on the output side of a final stage amplification unit. The final stage amplification unit power amplifies an input signal and outputs an amplified signal. A first matching circuit impedance converts the amplified signal input thereto at a first input impedance, and outputs a first impedance-converted signal at a first output impedance. A control unit that generates a control signal denoting signal path selection information. A switch unit selects one of at least two signal paths based on the control signal, passes the first impedance-converted signal at an on impedance through the selected path, and outputs the pass signal. A second matching circuit impedance converts a pass signal input thereto at a second input impedance, and outputs a second impedance-converted signal at a second output.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: March 16, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuki Tateoka, Masahiko Inamori, Shingo Matsuda, Kazuhiko Ohashi, Haruhiko Koizumi
  • Publication number: 20090251220
    Abstract: A bias circuit operable to supply a bias current to a first transistor includes: a second transistor having a collector terminal connected to a first power supply; a first resistance element having one end connected to an emitter terminal of the second transistor and having the other end connected to a base terminal of the first transistor; a second resistance element having one end connected to the emitter terminal of the second transistor and having the other end connected to ground potential; at least one third resistance element provided between a base terminal of the second transistor and a second power supply; and a plurality of temperature compensation circuits connected to the base terminal of the second transistor which are operable to control a base potential of the second transistor so that the potential falls as a temperature rises.
    Type: Application
    Filed: March 6, 2009
    Publication date: October 8, 2009
    Inventors: Shingo MATSUDA, Hirokazu MAKIHARA, Kazuki TATEOKA, Masahiko INAMORI
  • Publication number: 20090011723
    Abstract: A transmitting apparatus of the present invention includes an orthogonal modulator for generating a modulated signal by using an input signal; a polar-modulation-mode transmission circuit which includes a first power amplifier whose input terminal receives a phase component of the modulated signal generated by the orthogonal modulator and whose power supply terminal receives an amplitude component of the modulated signal generated by the orthogonal modulator, and which polar-modulates the modulated signal; an orthogonal-modulation-mode transmission circuit which includes a second power amplifier whose input terminal receives the modulated signal generated by the orthogonal modulator and whose power supply terminal receives a constant voltage, and which transmits the modulated signal; and a switch for connecting an output of the orthogonal modulator with an input of the polar-modulation-mode transmission circuit at the time of a high output, and for connecting the output of the orthogonal modulator and an inpu
    Type: Application
    Filed: July 1, 2008
    Publication date: January 8, 2009
    Inventors: Masahiko Inamori, Hirokazu Makihara, Kazuki Tateoka, Shingo Matsuda
  • Patent number: 7468636
    Abstract: A radio frequency power amplifier 1 includes a former-stage transistor 2, a latter-stage transistor 3, and an inter-stage matching circuit 4 for connecting the former-stage transistor 2 and the latter-stage transistor 3. The inter-stage matching circuit 4 includes a high-pass filter circuit including a transfer line m1, a capacitor C1 and a capacitor C2; and a transfer line m2 with which a passage phase of a secondary harmonic signal is 15 degrees or greater.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: December 23, 2008
    Assignee: Panasonic Corporation
    Inventors: Shingo Matsuda, Kazuki Tateoka, Hirokazu Makihara
  • Publication number: 20080297260
    Abstract: A radio-frequency power amplifier for preventing a final-stage HBT from being destroyed is provided. To this end, a radio-frequency multistage power amplifier of the present invention includes: a first amplification stage having a first hetero bipolar transistor of which collector output is detected; a second amplification stage which is prior to the first amplification stage and which has a second hetero bipolar transistor in which the detection result is reflected; a first resistor provided between a collector of the second hetero bipolar transistor and a power supply; and a protection circuit which is connected between a collector of the first hetero bipolar transistor and the collector of the second hetero bipolar transistor, detects output from the collector of the first hetero bipolar transistor, and reduces a voltage of the collector of the second hetero bipolar transistor in accordance with the detected output.
    Type: Application
    Filed: April 14, 2008
    Publication date: December 4, 2008
    Inventors: Hirokazu Makihara, Haruhiko Koizumi, Kazuki Tateoka, Masahiko Inamori, Shingo Matsuda
  • Publication number: 20080284539
    Abstract: A small, high performance, multifunctional high frequency circuit that is multiband and multimode compatible reduces loss from a switch formed on the output side of a final stage amplification unit. The final stage amplification unit power amplifies an input signal and outputs an amplified signal. A first matching circuit impedance converts the amplified signal input thereto at a first input impedance, and outputs a first impedance-converted signal at a first output impedance. A control unit that generates a control signal denoting signal path selection information. A switch unit selects one of at least two signal paths based on the control signal, passes the first impedance-converted signal at an on impedance through the selected path, and outputs the pass signal. A second matching circuit impedance converts a pass signal input thereto at a second input impedance, and outputs a second impedance-converted signal at a second output.
    Type: Application
    Filed: May 12, 2008
    Publication date: November 20, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuki TATEOKA, Masahiko Inamori, Shingo Matsuda, Kazuhiko Ohashi, Haruhiko Koizumi
  • Patent number: 7286018
    Abstract: The transistor circuit 1 includes a plurality of transistor cells 10 each having a transistor 11, a base ballast resistor 12, a capacitor 13, and an inductor 14. The transistors 11 have the respective collectors commonly connected to a collector terminal 1c of the transistor circuit 1 and the respective emitters commonly connected to an emitter terminal 1e thereof. Each base ballast resistor 12 is connected to bases of the transistor 11 at one end and to a base terminal 1b of the transistor circuit 1 at the other end. The capacitor 13 is serially connected to the inductor 14, thus to form a serial resonant circuit 15, which is connected in parallel with the base ballast resistor 12 and provided between the bases of the transistor 11 and the base terminal 1b of the transistor circuit 1 and connected thereto.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: October 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hirokazu Makihara, Kazuki Tateoka, Katsuhiko Kawashima, Shingo Matsuda
  • Publication number: 20070146077
    Abstract: A radio frequency power amplifier 1 includes a former-stage transistor 2, a latter-stage transistor 3, and an inter-stage matching circuit 4 for connecting the former-stage transistor 2 and the latter-stage transistor 3. The inter-stage matching circuit 4 includes a high-pass filter circuit including a transfer line m1, a capacitor C1 and a capacitor C2; and a transfer line m2 with which a passage phase of a secondary harmonic signal is 15 degrees or greater.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 28, 2007
    Inventors: Shingo Matsuda, Kazuki Tateoka, Hirokazu Makihara