Patents by Inventor Shingo Nakajima

Shingo Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240131777
    Abstract: A method of manufacturing a structure is provided in which a burr portion can be more reliably cut. In a burr portion shaping step, the burr portion is sucked to an engaging portion by a suction part to shape the burr portion along the engaging portion, and in a cutting step, ae movable portion is moved relative to first and second split molds with the burr portion being shaped along the engaging portion, thereby the burr portion is cut from a molded main body along a cutting line.
    Type: Application
    Filed: February 18, 2022
    Publication date: April 25, 2024
    Applicant: KYORAKU CO., LTD.
    Inventors: Yuki HARASAWA, Tadatoshi TANJI, Tatsuya FUKUDA, Takurou MATSUDA, Sho NAKAJIMA, Shingo NAGASHIMA
  • Publication number: 20230260997
    Abstract: A semiconductor device according to an embodiment includes: first and second gate electrodes; first and second spacer layers respectively covering the first and second gate electrodes; first and second liner layers respectively covering the first and second gate electrodes with the first and second spacer layers interposed therebetween; a first contact extending from above the first liner layer to below the first spacer layer and including a first conductive layer connected to the first gate electrode; and a second contact extending from above the second liner layer to below the second spacer layer and including a second conductive layer connected to the second gate electrode. The first conductive layer is in contact with the first spacer layer on the side surface via a first insulating layer covering a sidewall of the first conductive layer. The second conductive layer is in direct contact with the second spacer layer on the side surface.
    Type: Application
    Filed: July 14, 2022
    Publication date: August 17, 2023
    Applicant: Kioxia Corporation
    Inventors: Kota KATO, Shingo NAKAJIMA, Kaori KAWASAKI, Shoichi WATANABE
  • Patent number: 11709328
    Abstract: A plug connector is attachable with an optical fiber cable and is connectable with a receptacle connector. The receptacle connector comprises a receptacle shell. The plug connector comprises a front holder, a cable holding portion, a rear holder and a coupling member. The front holder is made of metal. The front holder is mated with the receptacle shell when the plug connector is connected with the receptacle connector. The cable holding portion is made of metal. The cable holding portion is configured to hold the optical fiber cable. The rear holder guards the cable holding portion. The rear holder comprises, at least in part, a thermal insulating portion made of non-metal material. The coupling member couples the front holder and the rear holder with each other. Each of the coupling member and the front holder is in contact with the rear holder only on the thermal insulating portion.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: July 25, 2023
    Assignee: Japan Aviation Electronics Industry, Limited
    Inventors: Yuichi Koreeda, Shingo Nakajima, Masaki Ishiguro
  • Publication number: 20220384466
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a peripheral circuit provided on the semiconductor substrate; and a stacked body provided above the peripheral circuit, which has a memory cell array. The peripheral circuit includes: a metal film including silicon; a silicide film stacked on the metal film; and a barrier metal film stacked on the silicide film.
    Type: Application
    Filed: December 6, 2021
    Publication date: December 1, 2022
    Applicant: Kioxia Corporation
    Inventors: Takashi IZUMI, Akitsugu HATAZAKI, Shingo NAKAJIMA
  • Patent number: 11482489
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 25, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
  • Publication number: 20220187554
    Abstract: A plug connector is attachable with an optical fiber cable and is connectable with a receptacle connector. The receptacle connector comprises a receptacle shell. The plug connector comprises a front holder, a cable holding portion, a rear holder and a coupling member. The front holder is made of metal. The front holder is mated with the receptacle shell when the plug connector is connected with the receptacle connector. The cable holding portion is made of metal. The cable holding portion is configured to hold the optical fiber cable. The rear holder guards the cable holding portion. The rear holder comprises, at least in part, a thermal insulating portion made of non-metal material. The coupling member couples the front holder and the rear holder with each other. Each of the coupling member and the front holder is in contact with the rear holder only on the thermal insulating portion.
    Type: Application
    Filed: March 12, 2020
    Publication date: June 16, 2022
    Applicant: Japan Aviation Electronics Industry, Limited
    Inventors: Yuichi KOREEDA, Shingo NAKAJIMA, Masaki ISHIGURO
  • Patent number: 11111946
    Abstract: Threaded parts such as bolts are rust-proofed by using a treatment liquid including a binder resin containing silica and at least one of a modified epoxy resin obtained by graft polymerization using a carboxylic acid-containing acrylic polymer as a side chain and a modified acrylic resin obtained by graft polymerization using a carboxylic acid-containing acrylic polymer as a side chain. By using this treatment liquid, coating treatment can be carried out at one time without need to use an organic solvent. There is an advantage that the friction coefficient does not increase even when tightening is repeated.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 7, 2021
    Assignee: Aoyama Seisakusho Co., Ltd.
    Inventors: Shingo Nakajima, Takashi Ito
  • Patent number: 10992085
    Abstract: A receptacle comprises a shell made of metal and a cage formed of one or more metal plates. The shell is attachable to a case made of metal. The cage is mountable on a board arranged in the case. The cage receives an internal module under a mated state where the receptacle is mated with a plug. The cage has a cage rear plate and is provided with a terminal made of metal and a contact portion made of metal. The terminal extends downward from the cage rear plate. The contact portion is nearer to the cage rear plate than to the front end of the cage in a front-rear direction. When the cage is mounted on the board and the shell is attached to the case, the shell covers the cage, the terminal is fixed to the board, and the contact portion is pressed against the shell.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 27, 2021
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Naoki Katagiyama, Masaki Ishiguro, Takayuki Tanaka, Akihiro Tosaki, Shingo Nakajima
  • Publication number: 20200373237
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
  • Patent number: 10840262
    Abstract: The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hanae Ishihara, Shingo Nakajima
  • Publication number: 20200319413
    Abstract: A receptacle comprises a shell made of metal and a cage formed of one or more metal plates. The shell is attachable to a case made of metal. The cage is mountable on a board arranged in the case. The cage receives an internal module under a mated state where the receptacle is mated with a plug. The cage has a cage rear plate and is provided with a terminal made of metal and a contact portion made of metal. The terminal extends downward from the cage rear plate. The contact portion is nearer to the cage rear plate than to the front end of the cage in a front-rear direction. When the cage is mounted on the board and the shell is attached to the case, the shell covers the cage, the terminal is fixed to the board, and the contact portion is pressed against the shell.
    Type: Application
    Filed: February 7, 2020
    Publication date: October 8, 2020
    Applicant: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Naoki KATAGIYAMA, Masaki ISHIGURO, Takayuki TANAKA, Akihiro TOSAKI, Shingo NAKAJIMA
  • Patent number: 10777501
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
  • Publication number: 20200176474
    Abstract: The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 4, 2020
    Inventors: Hanae ISHIHARA, Shingo NAKAJIMA
  • Patent number: 10423107
    Abstract: An object of the present invention is to provide a polyimide tube for a fixing belt, the polyimide tube having good toner fixability. A polyimide tube for a fixing belt of an image-forming apparatus according to the present invention includes a polyimide layer that contains a polyimide as a main component and a needle-like filler, the needle-like filler containing a carbon nanotube and needle-like titanium oxide. A product of a thermal diffusivity (m2/s) of the polyimide layer and a breaking elongation (%) of the polyimide layer in an axial direction is 35×10?7 or more. An orientation direction of the needle-like filler is preferably an axial direction or a circumferential direction.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 24, 2019
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC FINE POLYMER, INC.
    Inventors: Shingo Nakajima, Jun Sugawara, Masatoshi Ishikawa, Yoshitaka Ikeda, Kazuhiro Kizawa
  • Publication number: 20190287991
    Abstract: The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.
    Type: Application
    Filed: August 23, 2018
    Publication date: September 19, 2019
    Inventors: Hanae ISHIHARA, Shingo NAKAJIMA
  • Publication number: 20190287894
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Application
    Filed: July 3, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shingo NAKAJIMA, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
  • Patent number: 10365593
    Abstract: The present invention provides a self-heating fuser roller including a tubular resistor layer that generates heat by being supplied with electricity, in which the resistor layer has a plurality of slits. The slits are preferably disposed at regular intervals in a circumferential direction. The slits preferably extend in an axial direction. Preferably, the slits are not provided on both end edges in an axial direction. The slits preferably have an average width of 50 ?m or more and 2 mm or less. The slits preferably have an average interval of 30 ?m or more and 1 mm or less. The slits are preferably filled with a resin composition. The resistor layer preferably includes a resin matrix and a plurality of electrically conductive particles contained in the resin matrix.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: July 30, 2019
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, INC., SUMITOMO ELECTRIC FINE POLYMER, INC.
    Inventors: Shingo Nakajima, Jun Sugawara, Kazuhiro Kizawa, Yoshitaka Ikeda, Masato Tanaka
  • Patent number: 10323415
    Abstract: A pregrouted PC steel material (10) includes a 19-wire-twisted PC strand (1), a pregrouted layer (2) disposed on an outer periphery of the PC strand (1), and a sheath (3) configured to cover an outer periphery of the pregrouted layer (2). A filling resin (4) is filled between steel wires (side wires) (1b, 1c, 1d). Since the filling resin (4) does not exude to the pregrouted layer (2) before tensioning of the PC strand (10), an operation of tensioning the PC strand (1) is not hindered by curing of the pregrouted layer (2). In contrast, since the gap between the steel wires is reduced when the PC strand (1) is tensioned, the filling resin (4) flows out (exudes) from between the steel wires to the pregrouted layer (2) to cure the pregrouted layer (2) only after the reduction.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 18, 2019
    Assignee: Sumitomo (SEI) Steel Wire Corp.
    Inventors: Katsuhito Oshima, Masato Yamada, Yoshiyuki Matsubara, Kiminori Matsushita, Shuichi Tanaka, Jun Sugawara, Shingo Nakajima
  • Publication number: 20190128310
    Abstract: Threaded parts such as bolts are rust-proofed by using a treatment liquid including a binder resin containing silica and at least one of a modified epoxy resin obtained by graft polymerization using a carboxylic acid-containing acrylic polymer as a side chain and a modified acrylic resin obtained by graft polymerization using a carboxylic acid-containing acrylic polymer as a side chain. By using this treatment liquid, coating treatment can be carried out at one time without need to use an organic solvent. There is an advantage that the friction coefficient does not increase even when tightening is repeated.
    Type: Application
    Filed: December 19, 2018
    Publication date: May 2, 2019
    Applicant: AOYAMA SEISAKUSHO CO., LTD.
    Inventors: Shingo NAKAJIMA, Takashi ITO
  • Patent number: 10090312
    Abstract: According to the embodiments, the semiconductor memory device includes a semiconductor substrate, a first conducting layer, a semiconductor layer, a plurality of second conducting layer, and an electric charge accumulating layer. The first conducting layer is disposed on the semiconductor substrate via an insulating layer. The semiconductor layer is disposed on the first conducting layer and extends in a first direction above the semiconductor substrate. The plurality of the second conducting layers extends in a second direction intersecting with the first direction, and is laminated along the first direction via an insulating layer, and is disposed on the first conducting layer. The electric charge accumulating layer is disposed between the semiconductor layer and the plurality of second conducting layer. The semiconductor substrate includes an n type semiconductor region facing an end portion of the semiconductor layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shingo Nakajima, Hiroyasu Tanaka