Patents by Inventor Shingo Nakajima
Shingo Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12156404Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a peripheral circuit provided on the semiconductor substrate; and a stacked body provided above the peripheral circuit, which has a memory cell array. The peripheral circuit includes: a metal film including silicon; a silicide film stacked on the metal film; and a barrier metal film stacked on the silicide film.Type: GrantFiled: December 6, 2021Date of Patent: November 26, 2024Assignee: Kioxia CorporationInventors: Takashi Izumi, Akitsugu Hatazaki, Shingo Nakajima
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Publication number: 20240321247Abstract: An electronic keyboard instrument includes a main body case configured to include a sound emitting hole in a lower side, a keyboard provided inside the main body case, a sound emitting unit disposed on the lower side of the main body case in such a manner that a sound emitting port corresponding to the sound emitting hole is directed towards the keyboard, and a plate-shaped unit provided on an upper side of the sound emitting unit and configured to include a cutout formed in a portion corresponding to the sound emitting hole, and a communication path is provided inside the main body case, the communication path being configured to enable a sound emitted by the sound emitting unit to be emitted from an upper side of the keyboard towards an outside by way of the cutout in the plate-shaped unit.Type: ApplicationFiled: March 18, 2024Publication date: September 26, 2024Inventors: Hiroki AKAI, Naoto IMAMURA, Yuuki NAKAJIMA, Shingo FUKUSHIMA
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Publication number: 20240321250Abstract: An electronic instrument includes a substrate including a first area in which a connecting terminal is provided for connection with an external device and a second area which is larger than the first area, and a sheet metal including a contact configured to be electrically connected with the substrate in the second area of the substrate and including an opening provided in a position corresponding to a position where the connecting terminal is provided in the first area.Type: ApplicationFiled: March 19, 2024Publication date: September 26, 2024Inventors: Naoto IMAMURA, Yuuki NAKAJIMA, Shingo FUKUSHIMA, Takumi YOSHIDA, Masaru KONDO
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Patent number: 12053959Abstract: A polypropylene multilayer sheet includes: a biaxially oriented polypropylene layer F having a melting point TmF; and a biaxially oriented polypropylene layer N having a melting point TmN, the biaxially oriented polypropylene layer N and the biaxially oriented polypropylene layer F being alternately laminated, the polypropylene multilayer sheet having a thickness of 0.15 mm to 3.0 mm, wherein: TmF>TmN, a total number of layers is 3 to 11, the biaxially oriented polypropylene layer F is formed of a resin composition containing: a polypropylene-based resin as a component (A); and an inorganic filler as a component (B), a weight ratio of the component (B)/[the component (A)+the component (B)] is 0.5 to 60 wt %, the biaxially oriented polypropylene layer N is formed of a resin composition containing: a polypropylene-based resin as a component (a); and the component (B) as an optional component, and a weight ratio of the component (B)/[the component (a)+the component (B)] is 0 to 10 wt %.Type: GrantFiled: November 11, 2021Date of Patent: August 6, 2024Assignee: FP CORPORATION AND SUNALLOMER LTD.Inventors: Shingo Ueno, Takeshi Nakajima, Masayuki Ikeda
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Publication number: 20230260997Abstract: A semiconductor device according to an embodiment includes: first and second gate electrodes; first and second spacer layers respectively covering the first and second gate electrodes; first and second liner layers respectively covering the first and second gate electrodes with the first and second spacer layers interposed therebetween; a first contact extending from above the first liner layer to below the first spacer layer and including a first conductive layer connected to the first gate electrode; and a second contact extending from above the second liner layer to below the second spacer layer and including a second conductive layer connected to the second gate electrode. The first conductive layer is in contact with the first spacer layer on the side surface via a first insulating layer covering a sidewall of the first conductive layer. The second conductive layer is in direct contact with the second spacer layer on the side surface.Type: ApplicationFiled: July 14, 2022Publication date: August 17, 2023Applicant: Kioxia CorporationInventors: Kota KATO, Shingo NAKAJIMA, Kaori KAWASAKI, Shoichi WATANABE
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Patent number: 11709328Abstract: A plug connector is attachable with an optical fiber cable and is connectable with a receptacle connector. The receptacle connector comprises a receptacle shell. The plug connector comprises a front holder, a cable holding portion, a rear holder and a coupling member. The front holder is made of metal. The front holder is mated with the receptacle shell when the plug connector is connected with the receptacle connector. The cable holding portion is made of metal. The cable holding portion is configured to hold the optical fiber cable. The rear holder guards the cable holding portion. The rear holder comprises, at least in part, a thermal insulating portion made of non-metal material. The coupling member couples the front holder and the rear holder with each other. Each of the coupling member and the front holder is in contact with the rear holder only on the thermal insulating portion.Type: GrantFiled: March 12, 2020Date of Patent: July 25, 2023Assignee: Japan Aviation Electronics Industry, LimitedInventors: Yuichi Koreeda, Shingo Nakajima, Masaki Ishiguro
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Publication number: 20220384466Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a peripheral circuit provided on the semiconductor substrate; and a stacked body provided above the peripheral circuit, which has a memory cell array. The peripheral circuit includes: a metal film including silicon; a silicide film stacked on the metal film; and a barrier metal film stacked on the silicide film.Type: ApplicationFiled: December 6, 2021Publication date: December 1, 2022Applicant: Kioxia CorporationInventors: Takashi IZUMI, Akitsugu HATAZAKI, Shingo NAKAJIMA
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Patent number: 11482489Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.Type: GrantFiled: August 11, 2020Date of Patent: October 25, 2022Assignee: KIOXIA CORPORATIONInventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
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Publication number: 20220187554Abstract: A plug connector is attachable with an optical fiber cable and is connectable with a receptacle connector. The receptacle connector comprises a receptacle shell. The plug connector comprises a front holder, a cable holding portion, a rear holder and a coupling member. The front holder is made of metal. The front holder is mated with the receptacle shell when the plug connector is connected with the receptacle connector. The cable holding portion is made of metal. The cable holding portion is configured to hold the optical fiber cable. The rear holder guards the cable holding portion. The rear holder comprises, at least in part, a thermal insulating portion made of non-metal material. The coupling member couples the front holder and the rear holder with each other. Each of the coupling member and the front holder is in contact with the rear holder only on the thermal insulating portion.Type: ApplicationFiled: March 12, 2020Publication date: June 16, 2022Applicant: Japan Aviation Electronics Industry, LimitedInventors: Yuichi KOREEDA, Shingo NAKAJIMA, Masaki ISHIGURO
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Patent number: 11111946Abstract: Threaded parts such as bolts are rust-proofed by using a treatment liquid including a binder resin containing silica and at least one of a modified epoxy resin obtained by graft polymerization using a carboxylic acid-containing acrylic polymer as a side chain and a modified acrylic resin obtained by graft polymerization using a carboxylic acid-containing acrylic polymer as a side chain. By using this treatment liquid, coating treatment can be carried out at one time without need to use an organic solvent. There is an advantage that the friction coefficient does not increase even when tightening is repeated.Type: GrantFiled: December 19, 2018Date of Patent: September 7, 2021Assignee: Aoyama Seisakusho Co., Ltd.Inventors: Shingo Nakajima, Takashi Ito
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Patent number: 10992085Abstract: A receptacle comprises a shell made of metal and a cage formed of one or more metal plates. The shell is attachable to a case made of metal. The cage is mountable on a board arranged in the case. The cage receives an internal module under a mated state where the receptacle is mated with a plug. The cage has a cage rear plate and is provided with a terminal made of metal and a contact portion made of metal. The terminal extends downward from the cage rear plate. The contact portion is nearer to the cage rear plate than to the front end of the cage in a front-rear direction. When the cage is mounted on the board and the shell is attached to the case, the shell covers the cage, the terminal is fixed to the board, and the contact portion is pressed against the shell.Type: GrantFiled: February 7, 2020Date of Patent: April 27, 2021Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITEDInventors: Naoki Katagiyama, Masaki Ishiguro, Takayuki Tanaka, Akihiro Tosaki, Shingo Nakajima
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Publication number: 20200373237Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.Type: ApplicationFiled: August 11, 2020Publication date: November 26, 2020Applicant: Toshiba Memory CorporationInventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
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Patent number: 10840262Abstract: The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.Type: GrantFiled: February 10, 2020Date of Patent: November 17, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hanae Ishihara, Shingo Nakajima
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Publication number: 20200319413Abstract: A receptacle comprises a shell made of metal and a cage formed of one or more metal plates. The shell is attachable to a case made of metal. The cage is mountable on a board arranged in the case. The cage receives an internal module under a mated state where the receptacle is mated with a plug. The cage has a cage rear plate and is provided with a terminal made of metal and a contact portion made of metal. The terminal extends downward from the cage rear plate. The contact portion is nearer to the cage rear plate than to the front end of the cage in a front-rear direction. When the cage is mounted on the board and the shell is attached to the case, the shell covers the cage, the terminal is fixed to the board, and the contact portion is pressed against the shell.Type: ApplicationFiled: February 7, 2020Publication date: October 8, 2020Applicant: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITEDInventors: Naoki KATAGIYAMA, Masaki ISHIGURO, Takayuki TANAKA, Akihiro TOSAKI, Shingo NAKAJIMA
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Patent number: 10777501Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.Type: GrantFiled: July 3, 2018Date of Patent: September 15, 2020Assignee: Toshiba Memory CorporationInventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
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Publication number: 20200176474Abstract: The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.Type: ApplicationFiled: February 10, 2020Publication date: June 4, 2020Inventors: Hanae ISHIHARA, Shingo NAKAJIMA
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Patent number: 10423107Abstract: An object of the present invention is to provide a polyimide tube for a fixing belt, the polyimide tube having good toner fixability. A polyimide tube for a fixing belt of an image-forming apparatus according to the present invention includes a polyimide layer that contains a polyimide as a main component and a needle-like filler, the needle-like filler containing a carbon nanotube and needle-like titanium oxide. A product of a thermal diffusivity (m2/s) of the polyimide layer and a breaking elongation (%) of the polyimide layer in an axial direction is 35×10?7 or more. An orientation direction of the needle-like filler is preferably an axial direction or a circumferential direction.Type: GrantFiled: July 7, 2015Date of Patent: September 24, 2019Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC FINE POLYMER, INC.Inventors: Shingo Nakajima, Jun Sugawara, Masatoshi Ishikawa, Yoshitaka Ikeda, Kazuhiro Kizawa
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Publication number: 20190287991Abstract: The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.Type: ApplicationFiled: August 23, 2018Publication date: September 19, 2019Inventors: Hanae ISHIHARA, Shingo NAKAJIMA
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Publication number: 20190287894Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.Type: ApplicationFiled: July 3, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Shingo NAKAJIMA, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
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Patent number: 10365593Abstract: The present invention provides a self-heating fuser roller including a tubular resistor layer that generates heat by being supplied with electricity, in which the resistor layer has a plurality of slits. The slits are preferably disposed at regular intervals in a circumferential direction. The slits preferably extend in an axial direction. Preferably, the slits are not provided on both end edges in an axial direction. The slits preferably have an average width of 50 ?m or more and 2 mm or less. The slits preferably have an average interval of 30 ?m or more and 1 mm or less. The slits are preferably filled with a resin composition. The resistor layer preferably includes a resin matrix and a plurality of electrically conductive particles contained in the resin matrix.Type: GrantFiled: July 25, 2016Date of Patent: July 30, 2019Assignees: SUMITOMO ELECTRIC INDUSTRIES, INC., SUMITOMO ELECTRIC FINE POLYMER, INC.Inventors: Shingo Nakajima, Jun Sugawara, Kazuhiro Kizawa, Yoshitaka Ikeda, Masato Tanaka