Patents by Inventor Shingo NAKAZAWA
Shingo NAKAZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096429Abstract: A semiconductor storage device includes a first word line, a second word line, a first select gate line, a second select gate line, a third select gate line, a fourth select gate line, a first memory pillar including a first memory cell connected to the first word line, a first select transistor connected to the first select gate line, a second memory cell connected to the second word line, and a second select transistor connected to the second select gate line, and a logic control circuit configured to perform a read operation to read threshold voltages of the first and second memory cells, respectively. The logic control circuit independently controls the first to fourth select gate lines during the read operation to turn the select transistors electrically connected to memory cells other than the memory cell to be read to off state.Type: ApplicationFiled: August 29, 2023Publication date: March 21, 2024Inventors: Shingo NAKAZAWA, Yuki INUZUKA
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Patent number: 11929123Abstract: A semiconductor memory device includes first conductive layers, second conductive layers, a first semiconductor layer, a charge storage layer, and a first wiring. The semiconductor memory device is configured to execute an erase operation including a first and a second erase loop. In the first erase loop, the semiconductor memory device applies a first voltage to at least a part of the first conductive layers and at least a part of the second conductive layers and applies an erase voltage larger than the first voltage to the first wiring. In the second erase loop, the semiconductor memory device applies the first voltage to at least a part of the first conductive layers, applies a second voltage larger than the first voltage to at least apart of the second conductive layers, and applies the erase voltage to the first wiring.Type: GrantFiled: December 10, 2021Date of Patent: March 12, 2024Assignee: KIOXIA CORPORATIONInventor: Shingo Nakazawa
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Patent number: 11727995Abstract: A semiconductor memory device includes: first conductive layers; second conductive layers; a first semiconductor layer disposed between the first conductive layers and the second conductive layers; a charge storage layer that includes a first part disposed between the plurality of first conductive layers and the first semiconductor layer and a second part disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The semiconductor memory device is configured such that a read operation and a first operation performed before the read operation are performable. In the first operation: a first voltage is supplied to the first wiring; and a second voltage smaller than the first voltage is supplied to an n-th second conductive layer counted from the one side in the first direction.Type: GrantFiled: September 7, 2021Date of Patent: August 15, 2023Assignee: Kioxia CorporationInventor: Shingo Nakazawa
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Patent number: 11538536Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, second conductive layers arranged in the first direction, a first semiconductor layer disposed therebetween, a charge storage layer, a first wiring electrically connected to the first semiconductor layer, and first and second transistors connected to the first and the second conductive layers. In the semiconductor memory device, in an erase operation, a first voltage is supplied to at least a part of the first conductive layers, an erase voltage larger than the first voltage is supplied to the first wiring, and a first signal voltage is supplied to at least a part of the second transistors. The first signal voltage turns OFF the second transistor.Type: GrantFiled: March 12, 2021Date of Patent: December 27, 2022Assignee: Kioxia CorporationInventors: Shingo Nakazawa, Takashi Maeda
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Publication number: 20220406384Abstract: A semiconductor memory device includes first conductive layers, second conductive layers, a first semiconductor layer, a charge storage layer, and a first wiring. The semiconductor memory device is configured to execute an erase operation including a first and a second erase loop. In the first erase loop, the semiconductor memory device applies a first voltage to at least a part of the first conductive layers and at least a part of the second conductive layers and applies an erase voltage larger than the first voltage to the first wiring. In the second erase loop, the semiconductor memory device applies the first voltage to at least a part of the first conductive layers, applies a second voltage larger than the first voltage to at least apart of the second conductive layers, and applies the erase voltage to the first wiring.Type: ApplicationFiled: December 10, 2021Publication date: December 22, 2022Applicant: KIOXIA CORPORATIONInventor: Shingo NAKAZAWA
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Publication number: 20220310175Abstract: A semiconductor memory device includes: first conductive layers; second conductive layers; a first semiconductor layer disposed between the first conductive layers and the second conductive layers; a charge storage layer that includes a first part disposed between the plurality of first conductive layers and the first semiconductor layer and a second part disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The semiconductor memory device is configured such that a read operation and a first operation performed before the read operation are performable. In the first operation: a first voltage is supplied to the first wiring; and a second voltage smaller than the first voltage is supplied to an n-th second conductive layer counted from the one side in the first direction.Type: ApplicationFiled: September 7, 2021Publication date: September 29, 2022Applicant: Kioxia CorporationInventor: Shingo NAKAZAWA
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Publication number: 20220084608Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, second conductive layers arranged in the first direction, a first semiconductor layer disposed therebetween, a charge storage layer, a first wiring electrically connected to the first semiconductor layer, and first and second transistors connected to the first and the second conductive layers. In the semiconductor memory device, in an erase operation, a first voltage is supplied to at least a part of the first conductive layers, an erase voltage larger than the first voltage is supplied to the first wiring, and a first signal voltage is supplied to at least a part of the second transistors. The first signal voltage turns OFF the second transistor.Type: ApplicationFiled: March 12, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Shingo NAKAZAWA, Takashi MAEDA
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Patent number: 10796757Abstract: A semiconductor storage device includes interconnections in a first layer and a second layer, a first memory cell between a first and a second interconnection, and a dummy memory cell between the first interconnection and a third interconnection. A controller applies a first voltage of a first polarity to the first interconnection and a second voltage of a second polarity opposite the first polarity to the second interconnection at a first time. The controller applies a third voltage at a second time after the first time to the first interconnection. The third voltage having a smaller magnitude smaller than first voltage. The controller applies a fourth voltage to the third interconnection at the second time. The fourth voltage has a magnitude larger than the third voltage but smaller than the first voltage.Type: GrantFiled: August 30, 2019Date of Patent: October 6, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Shingo Nakazawa
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Publication number: 20200294585Abstract: A semiconductor storage device includes interconnections in a first layer and a second layer, a first memory cell between a first and a second interconnection, and a dummy memory cell between the first interconnection and a third interconnection. A controller applies a first voltage of a first polarity to the first interconnection and a second voltage of a second polarity opposite the first polarity to the second interconnection at a first time. The controller applies a third voltage at a second time after the first time to the first interconnection. The third voltage having a smaller magnitude smaller than first voltage. The controller applies a fourth voltage to the third interconnection at the second time. The fourth voltage has a magnitude larger than the third voltage but smaller than the first voltage.Type: ApplicationFiled: August 30, 2019Publication date: September 17, 2020Inventor: Shingo NAKAZAWA
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Patent number: 10566054Abstract: According to one embodiment, a semiconductor memory device includes a memory cell having a variable resistance unit, a first selector, and a second selector. The first and second selectors are connected in series with the variable resistance unit and have different switching characteristics from one another. A control unit is provided to write data to the memory cell by setting a resistance state of the variable resistance unit and to read data from the memory cell according to the resistance state of the variable resistance unit.Type: GrantFiled: August 27, 2018Date of Patent: February 18, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shingo Nakazawa, Takayuki Miyazaki
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Publication number: 20190295639Abstract: According to one embodiment, a semiconductor memory device includes a memory cell having a variable resistance unit, a first selector, and a second selector. The first and second selectors are connected in series with the variable resistance unit and have different switching characteristics from one another. A control unit is provided to write data to the memory cell by setting a resistance state of the variable resistance unit and to read data from the memory cell according to the resistance state of the variable resistance unit.Type: ApplicationFiled: August 27, 2018Publication date: September 26, 2019Inventors: Shingo NAKAZAWA, Takayuki MIYAZAKI
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Patent number: 10347690Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.Type: GrantFiled: February 26, 2018Date of Patent: July 9, 2019Assignee: Toshiba Memory CorporationInventors: Shingo Nakazawa, Tsuneo Inaba, Hiroyuki Takenaka
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Publication number: 20190081101Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. one of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.Type: ApplicationFiled: February 26, 2018Publication date: March 14, 2019Inventors: Shingo NAKAZAWA, Tsuneo INABA, Hiroyuki TAKENAKA