Patents by Inventor Shingo Saigo

Shingo Saigo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7940362
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: May 10, 2011
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Patent number: 7609350
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: October 27, 2009
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Publication number: 20070013853
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Application
    Filed: September 20, 2006
    Publication date: January 18, 2007
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Publication number: 20070013852
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Application
    Filed: September 20, 2006
    Publication date: January 18, 2007
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Patent number: 7130009
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: October 31, 2006
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Publication number: 20040070718
    Abstract: A display portion is divided by scan lines and signal lines into sections where pixels are provided. Contact holes each for connecting common wiring and a common electrode together are not formed for all the pixels, but decimated so as to be arranged in zigzags.
    Type: Application
    Filed: September 15, 2003
    Publication date: April 15, 2004
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Shingo Saigo, Takasuke Hayase, Makoto Horinouchi, Hideto Motoshima, Akitoshi Maeda
  • Patent number: 6514800
    Abstract: In a method of manufacturing a thin-film transistor, when channel etching for removing predetermined portions of an ohmic layer and a diffusion layer thereof by plasma etching is to be performed, a surface of a semiconductor layer of a channel portion is formed to have predetermined steps.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: February 4, 2003
    Assignee: NEC Corporation
    Inventor: Shingo Saigo
  • Publication number: 20020031872
    Abstract: In a method of manufacturing a thin-film transistor, when channel etching for removing predetermined portions of an ohmic layer and a diffusion layer thereof by plasma etching is to be performed, a surface of a semiconductor layer of a channel portion is formed to have predetermined steps.
    Type: Application
    Filed: September 10, 2001
    Publication date: March 14, 2002
    Applicant: NEC Corporation
    Inventor: Shingo Saigo