Patents by Inventor SHINGO SETO

SHINGO SETO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Signal transmission device and management system
    Patent number: 10716289
    Abstract: [Object] To provide a signal transmission device and management system which are capable of transmitting a signal including information of an attachment target or information of the surrounding of an attachment target.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: July 21, 2020
    Assignee: Sony Corporation
    Inventors: Hideo Niikura, Masakazu Yajima, Junya Matsui, Tamotsu Kiyakawauchi, Hiromitsu Komatsu, Chisako Kajihara, Shingo Seto, Nobuharu Murashima, Masaaki Masuda
  • SIGNAL TRANSMISSION DEVICE AND MANAGEMENT SYSTEM
    Publication number: 20190380306
    Abstract: [Object] To provide a signal transmission device and management system which are capable of transmitting a signal including information of an attachment target or information of the surrounding of an attachment target.
    Type: Application
    Filed: March 8, 2017
    Publication date: December 19, 2019
    Applicant: Sony Corporation
    Inventors: Hideo Niikura, Masakazu Yajima, Junya Matsui, Tamotsu Kiyakawauchi, Hiromitsu Komatsu, Chisako Kajihara, Shingo Seto, Nobuharu Murashima, Masaaki Masuda
  • Phase-locked loop and frequency synthesizer
    Patent number: 10305493
    Abstract: A phase-locked loop according to the present disclosure includes a reference-phase generation circuit that sequentially generates a reference phase value, and an oscillating circuit that generates a first clock on a basis of a difference between the reference phase value and a feedback phase value. The phase-locked loop further includes a signal generation circuit that generates, on a basis of the first clock, a plurality of second clocks varying in phase, and generates a third clock by switching the plurality of second clocks a plurality of times in each of cycle periods each corresponding to one cycle of the reference clock. The phase-locked loop further includes a phase detection circuit that determines a phase value of the third clock and outputs the determined phase value as the feedback phase value.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 28, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shingo Seto, Satoshi Suda
  • PHASE-LOCKED LOOP AND FREQUENCY SYNTHESIZER
    Publication number: 20170237443
    Abstract: A phase-locked loop according to the present disclosure includes a reference-phase generation circuit that sequentially generates a reference phase value, and an oscillating circuit that generates a first clock on a basis of a difference between the reference phase value and a feedback phase value. The phase-locked loop further includes a signal generation circuit that generates, on a basis of the first clock, a plurality of second clocks varying in phase, and generates a third clock by switching the plurality of second clocks a plurality of times in each of cycle periods each corresponding to one cycle of the reference clock. The phase-locked loop further includes a phase detection circuit that determines a phase value of the third clock and outputs the determined phase value as the feedback phase value.
    Type: Application
    Filed: October 1, 2015
    Publication date: August 17, 2017
    Inventors: SHINGO SETO, SATOSHI SUDA