Abstract: A multilayer wiring substrate includes a first wiring substrate including a plurality of stacked layers made of a thermo setting resin and having a wiring layer formed between each adjacent layer of the layers in a state in contact with the adjacent layers, a second wiring substrate made of a ceramic, and a joining layer disposed between a back surface of the first wiring substrate and a front surface of the second wiring substrate and configured to join the first wiring substrate and the second wiring substrate to each other, wherein at least a surface of the joining layer adjacent to the second wiring substrate is made of a thermo plastic resin.

Abstract: Bonding strength and yield can be enhanced by providing a mating pair of a convex bonding surface and a concave bonding surface. The convex bonding surface can be provided by employing a conductive barrier layer having a higher electrochemical potential than copper. The concave bonding surface can be provided by employing a conductive barrier layer having a lower electrochemical potential than copper. Alternatively additionally, a copper material portion in a bonding pad may include at least 10% volume fraction of (200) copper grains to provide high volume expansion toward a mating copper material portion. The mating copper material portion may be formed with at least 95% volume fraction of (111) copper grains to provide high surface diffusivity, or may be formed with at least 10% volume fraction of (200) copper grains to provide high volume expansion.

Abstract: A bonded assembly includes a first semiconductor die containing first semiconductor devices and a first bonding pad embedded within a first silicon oxide layer, where the first bonding pad includes a first copper containing portion, a second semiconductor die containing second semiconductor devices and a second bonding pad that is embedded within a second silicon oxide layer and is bonded to the first bonding pad via metal-to-metal bonding, where the second bonding pad includes a second copper containing portion, and at least one metal silicon oxide layer interposed between the first bonding pad and the second silicon oxide layer. In one embodiment, the at least one metal silicon oxide layer is a manganese silicon oxide layer.

Abstract: A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion of

Abstract: A bonded assembly includes a first semiconductor die that includes first metallic bonding structures embedded within a first bonding-level dielectric layer, and a second semiconductor die that includes second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding. One of the first metallic bonding structures a pad portion, and a via portion located between the pad portion and the first semiconductor device, the via portion having second tapered sidewalls.

Abstract: A multilayer wiring substrate includes a first wiring substrate including a plurality of stacked layers made of a thermo setting resin and having a wiring layer formed between each adjacent layer of the layers in a state in contact with the adjacent layers, a second wiring substrate made of a ceramic, and a joining layer disposed between a back surface of the first wiring substrate and a front surface of the second wiring substrate and configured to join the first wiring substrate and the second wiring substrate to each other, wherein at least a surface of the joining layer adjacent to the second wiring substrate is made of a thermo plastic resin.

Abstract: A metal layer is formed by vapor deposition or sputtering on an AlN substrate. Since there are irregularities on the surface of the substrate, irregularities are also formed on the surface of the metal layer. Subsequently, irregularities on the surface of the metal layer are removed and flattened in a mirror state by grinding the surface of the metal layer. Then, a dielectric layer is formed on the metal layer by alternately forming a SiO2 film and a TiO2 film through CVD. Next, an electrode layer is formed in a predetermined pattern by vapor deposition and lift-off on the dielectric layer. Since the surface of the metal layer is flattened in a mirror state, reflectance is high on that surface. As a result, the emission efficiency of the light-emitting device can be improved.

Abstract: To remove a deteriorated layer generated in forming a scribing trench by laser irradiation. A scribing trench is formed by irradiating a laser beam along a device dividing line on the rear surface of a substrate. At this time, a deteriorated layer is formed on the bottom surface or side surface of the scribing trench. Next, a protective film is formed so as to cover the entire top surface of the device structure, and the deteriorated layer is removed by wet etching. Wet etching is performed by alternately repeating BHF (buffered hydrofluoric acid) wet etching and MEA (monoethanolamine) wet etching several times.

Abstract: An n-side flattening electrode and a p-side flattening electrode are formed apart from each other on a predetermined region on an insulating film. Recesses are formed according to the level difference due to holes on the surfaces of the n-side flattening electrode and the p-side flattening electrode. Subsequently, the surfaces of the n-side flattening electrode and the p-side flattening electrode are ground until the surfaces become flat. After removal of oxide film, an n-side junction electrode and a p-side junction electrode are formed on the n-side flattening electrode and the p-side flattening electrode, respectively. Since the surfaces of the n-side flattening electrode and the p-side flattening electrode are flattened, the surfaces of the n-side junction electrode and the p-side junction electrode become flat so that the thickness is uniform.

Abstract: A sacrificial layer is formed on a region for forming the reflective electrode later on the p-type layer, Subsequently, a part of the p-type layer is dry etched to expose an n-type layer. Then, a resist layer having an opening is formed through photolithography on the p-type layer and the n-type layer exposed in the previous step. The opening has a pattern to enclose the sacrificial layer in a plan view. Next, the sacrificial layer is wet etched using a buffered hydrofluoric acid to remove the entire sacrifice layer. Subsequently, a reflective film is formed by sputtering on the p-type layer and the resist layer. Next, the resist layer is removed using a resist stripper, and only the reflective film on the p-type layer is left to form the reflective electrode.

Abstract: A transparent electrode is formed on a region for forming a reflective electrode later on the p-type layer. Subsequently, a part of the surface of the p-type layer is dry etched to expose the n-type layer. On the p-type layer and the n-type layer exposed in the previous step, a resist layer with an opening is formed through photolithography. The opening has a pattern in which the center of the transparent electrode is exposed and the ends of the opening are covered with the resist layer. Next, the transparent electrode is wet etched. A reflective film is formed on the p-type layer and the resist layer, to remove the resist layer. Thus, only the reflective film on the p-type layer is left to form a reflective electrode. Then, a cover metal layer is continuously formed over the reflective electrode and the transparent electrode.

Abstract: To remove a deteriorated layer generated in forming a scribing trench by laser irradiation. A scribing trench is formed by irradiating a laser beam along a device dividing line on the rear surface of a substrate. At this time, a deteriorated layer is formed on the bottom surface or side surface of the scribing trench. Next, a protective film is formed so as to cover the entire top surface of the device structure, and the deteriorated layer is removed by wet etching. Wet etching is performed by alternately repeating BHF (buffered hydrofluoric acid) wet etching and MEA (monoethanolamine) wet etching several times.

Abstract: An n-side flattening electrode and a p-side flattening electrode are formed apart from each other on a predetermined region on an insulating film. Recesses are formed according to the level difference due to holes on the surfaces of the n-side flattening electrode and the p-side flattening electrode. Subsequently, the surfaces of the n-side flattening electrode and the p-side flattening electrode are ground until the surfaces become flat. After removal of oxide film, an n-side junction electrode and a p-side junction electrode are formed on the n-side flattening electrode and the p-side flattening electrode, respectively. Since the surfaces of the n-side flattening electrode and the p-side flattening electrode are flattened, the surfaces of the n-side junction electrode and the p-side junction electrode become flat so that the thickness is uniform.

Abstract: A metal layer is formed by vapor deposition or sputtering on an AlN substrate. Since there are irregularities on the surface of the substrate, irregularities are also formed on the surface of the metal layer. Subsequently, irregularities on the surface of the metal layer are removed and flattened in a mirror state by grinding the surface of the metal layer. Then, a dielectric layer is formed on the metal layer by alternately forming a SiO2 film and a TiO2 film through CVD. Next, an electrode layer is formed in a predetermined pattern by vapor deposition and lift-off on the dielectric layer. Since the surface of the metal layer is flattened in a mirror state, reflectance is high on that surface. As a result, the emission efficiency of the light-emitting device can be improved.

Abstract: A planar light source comprises a light guide plate and a light-emitting apparatus disposed on a lateral surface of the light guide plate. The light-emitting apparatus comprises a light-emitting device, a case, and a sealing resin. The light-emitting device has a rectangular shape in a plan view, a long-side lateral surface of a semiconductor layer is reversed tapered having an inclination such that a cross section area increases in a direction parallel to a main surface of a sapphire substrate as a distance from the sapphire substrate increases, and a short-side lateral surface is perpendicular to the main surface of the sapphire substrate. A short-side and a long-side direction of the light-emitting device are perpendicular and parallel to the planar main surface of the light guide plate, respectively. The main surface of the light-emitting device is parallel to the lateral surface of the light guide plate.

Abstract: To provide a light-emitting unit having a semiconductor light-emitting device with a good responsiveness and a sufficient light emission quantity. The light-emitting unit comprises a plurality of semiconductor light-emitting devices, an n-wiring electrode and a p-wiring electrode respectively connecting the semiconductor light-emitting devices in parallel, an n-pad electrode connected to the n-wiring electrode, and a p-pad electrode connected to the p-wiring electrode. At least one of the Group III nitride semiconductor light-emitting devices has a light emission volume of 1 ?m3 to 14 ?m3.

Abstract: The present invention provides a light-emitting device suppressing the reduction in the light output while improving the response speed. As shown in FIG. 1, the light-emitting device comprises four square element regions arranged with the sides of the element regions aligned in a two by two lattice. The light-emitting regions are disposed in the vicinity of corners at the center side of the element regions, and the light-emitting regions are localized in the vicinity of the center in the entire element region. A plane pattern of each of the light-emitting regions is formed so that plane patterns of p-electrodes and n-electrodes are not disposed in a region sandwiched by the light-emitting regions.

Abstract: The present invention provides a method for producing a semiconductor light-emitting device in which fine protrusions and recesses are formed on a bottom surface between the protrusions on a surface of a substrate. The method comprises forming a first resist pattern on a nitrogen surface of the substrate, forming a plurality of first protrusions on the nitrogen surface of the substrate, and forming a plurality of second protrusions on the nitrogen surface of the transparent nitride-based substrate. In forming the first protrusions, the plurality of first protrusions and a bottom surface between the first protrusions are formed by dry etching. In forming the second protrusions, the plurality of second protrusions having a height lower than the height of the first protrusions are formed on the bottom surface by wet etching without removing the first resist pattern subjected to dry etching.

Abstract: A sacrificial layer is formed on a region for forming the reflective electrode later on the p-type layer, Subsequently, a part of the p-type layer is dry etched to expose an n-type layer. Then, a resist layer having an opening is formed through photolithography on the p-type layer and the n-type layer exposed in the previous step. The opening has a pattern to enclose the sacrificial layer in a plan view. Next, the sacrificial layer is wet etched using a buffered hydrofluoric acid to remove the entire sacrifice layer. Subsequently, a reflective film is formed by sputtering on the p-type layer and the resist layer. Next, the resist layer is removed using a resist stripper, and only the reflective film on the p-type layer is left to form the reflective electrode.

Abstract: A transparent electrode is formed on a region for forming a reflective electrode later on the p-type layer. Subsequently, a part of the surface of the p-type layer is dry etched to expose the n-type layer. On the p-type layer and the n-type layer exposed in the previous step, a resist layer with an opening is formed through photolithography. The opening has a pattern in which the center of the transparent electrode is exposed and the ends of the opening are covered with the resist layer. Next, the transparent electrode is wet etched. A reflective film is formed on the p-type layer and the resist layer, to remove the resist layer. Thus, only the reflective film on the p-type layer is left to form a reflective electrode. Then, a cover metal layer is continuously formed over the reflective electrode and the transparent electrode.