Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

Abstract: A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.

Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.

Abstract: A memory device includes: in-memory operation units to perform in-memory processing of an operation pipelined in multi-pipeline stages; memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank performing an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the in-memory operation units, the memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.

Abstract: A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.

Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

Abstract: A processor-implemented includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

Abstract: A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.

Abstract: A memory device includes a memory bank including one or more bank arrays, a PIM circuit configured to perform an operation logic processing operation, and an instruction memory including first to mth instruction queue segments configured in a circular instruction queue to store instructions provided by a host, where instructions stored in the first to mth instruction queue segments are executed in response to an operation request from the host and each new instruction provided by the host is updated over a completely executed instruction in the circular instruction queue.

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

Abstract: A three-dimensional stacked memory device includes a buffer die having a plurality of core die memories stacked thereon. The buffer die is configured as a buffer to occupy a first space in the buffer die. The first memory module, disposed in a second space unoccupied by the buffer, is configured to operate as a cache of the core die memories. The controller is configured to detect a fault in a memory area corresponding to a cache line in the core die memories based on a result of a comparison between data stored in the cache line and data stored in the memory area corresponding to the cache line in the core die memories. The second memory module, disposed in a third space unoccupied by the buffer and the first memory module, is configured to replace the memory area when the fault is detected in the memory area.

Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.

Abstract: A method of quantizing parameters of a neural network includes calculating, for each of the parameters, a bit shift value indicating a degree outside a bit range of a fixed-point format for quantizing the parameters, updating the fixed-point format based on the calculated bit shift values of the parameters, and quantizing parameters updated in a learning or inference process according to the updated fixed-point format.

Abstract: Provided is a processor implemented method that includes performing training or an inference operation with a neural network by obtaining a parameter for the neural network in a floating-point format, applying a fractional length of a fixed-point format to the parameter in the floating-point format, performing an operation with an integer arithmetic logic unit (ALU) to determine whether to round off a fixed point based on a most significant bit among bit values to be discarded after a quantization process, and performing an operation of quantizing the parameter in the floating-point format to a parameter in the fixed-point format, based on a result of the operation with the ALU.