Patents by Inventor Shin-Hee Han
Shin-Hee Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942956Abstract: Provided is a time-to-digital converter, comprising a phase frequency detector configured to receive a phase-locked loop input clock and a feedback clock, a ring oscillator configured to perform oscillation with multi-phase clocks of a first period, a counter array configured to count the number of oscillations in which the ring oscillator oscillates in a first period by the number of positive integers during the first pulse width, a multiplexer configured to divide the first period into a plurality of zones using edge information of the multi-phase clocks of the ring oscillator, and selects and outputs voltage information of a plurality of neighboring phase clocks included in a first zone from the plurality of zones, an analog-to-digital converter, a calibrator, and a first adder, wherein the calibrator comprises, an offset lookup table generation circuit, a gain-corrected analog-to-digital conversion output generator, and a second adder.Type: GrantFiled: August 11, 2022Date of Patent: March 26, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Min Seob Lee, Shin Woong Kim, Joon Hee Lee, Sang Wook Han
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Patent number: 11417833Abstract: A MRAM device includes a first insulating interlayer on a substrate including a cell region and a peripheral region, lower electrode contacts extending through the first insulating interlayer of the cell region, a first structure on each of the lower electrode contacts, the first structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked, and a capping layer covering surfaces of the first insulating interlayer and the first structure in the cell and peripheral regions, wherein an upper surface of the capping layer on the first insulating interlayer in the peripheral region is higher than an upper surface of the capping layer on the first insulating interlayer between the first structures in the cell region.Type: GrantFiled: September 1, 2020Date of Patent: August 16, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo-Jin Kim, Shin-Hee Han
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Publication number: 20220130884Abstract: An image sensor including a variable resistance element is provided. The image sensor comprises first and second chips having first and second connecting structures; and a contact plug connecting the first and second chips. The first chip includes a photoelectric conversion element. The second chip includes a first variable resistance element. The contact plug extends from the first surface of the first semiconductor substrate to connect the first and second connecting structures.Type: ApplicationFiled: August 4, 2021Publication date: April 28, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Dae Shik KIM, Min-Sun KEEL, Hoon Joo NA, Kang Ho LEE, Kil Ho LEE, Sang Kil LEE, Jung Hyuk LEE, Shin Hee HAN
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Publication number: 20200403145Abstract: A MRAM device includes a first insulating interlayer on a substrate including a cell region and a peripheral region, lower electrode contacts extending through the first insulating interlayer of the cell region, a first structure on each of the lower electrode contacts, the first structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked, and a capping layer covering surfaces of the first insulating interlayer and the first structure in the cell and peripheral regions, wherein an upper surface of the capping layer on the first insulating interlayer in the peripheral region is higher than an upper surface of the capping layer on the first insulating interlayer between the first structures in the cell region.Type: ApplicationFiled: September 1, 2020Publication date: December 24, 2020Inventors: Woo-Jin KIM, Shin-Hee HAN
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Patent number: 10797228Abstract: A MRAM device includes a first insulating interlayer on a substrate including a cell region and a peripheral region, lower electrode contacts extending through the first insulating interlayer of the cell region, a first structure on each of the lower electrode contacts, the first structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked, and a capping layer covering surfaces of the first insulating interlayer and the first structure in the cell and peripheral regions, wherein an upper surface of the capping layer on the first insulating interlayer in the peripheral region is higher than an upper surface of the capping layer on the first insulating interlayer between the first structures in the cell region.Type: GrantFiled: March 27, 2019Date of Patent: October 6, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo-Jin Kim, Shin-Hee Han
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Publication number: 20200098977Abstract: A MRAM device includes a first insulating interlayer on a substrate including a cell region and a peripheral region, lower electrode contacts extending through the first insulating interlayer of the cell region, a first structure on each of the lower electrode contacts, the first structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked, and a capping layer covering surfaces of the first insulating interlayer and the first structure in the cell and peripheral regions, wherein an upper surface of the capping layer on the first insulating interlayer in the peripheral region is higher than an upper surface of the capping layer on the first insulating interlayer between the first structures in the cell region.Type: ApplicationFiled: March 27, 2019Publication date: March 26, 2020Inventors: Woo-Jin KIM, Shin-Hee HAN
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Publication number: 20170069832Abstract: A magnetoresistive memory device includes a lower electrode on a substrate, a magnetic tunnel junction (MTJ) structure on the lower electrode, and a mask structure. The MTJ structure includes a lower magnetic pattern, a tunnel barrier pattern, and an upper magnetic pattern which are stacked. The mask structure includes an upper electrode and a sidewall capping pattern enclosing a sidewall of the upper electrode.Type: ApplicationFiled: June 17, 2016Publication date: March 9, 2017Inventors: Yong-Jae KIM, Woo-Jin KIM, Ki-Seok SUH, Shin-Hee HAN, Gwan-Hyeob KOH
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Patent number: 9087769Abstract: A magnetic memory device is provided. The magnetic memory device may include a plurality of word lines extending along a direction crossing a plurality of active regions and at least one source line connected to a plurality of first active regions arranged on a level that is lower than the upper surface of a substrate. A plurality of contact pads may be connected to a plurality of second active regions and a plurality of buried contact plugs may be connected to the plurality of second active regions via the plurality of contact pads. Said buried contact pads may further be arranged in a hexagonal array structure. A plurality of variable resistance structures may be connected to the plurality of second active regions and arranged in a hexagonal array structure.Type: GrantFiled: July 22, 2014Date of Patent: July 21, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-kwan Kim, Dae-eun Jeong, Shin-hee Han
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Publication number: 20150061054Abstract: A magnetic memory device is provided. The magnetic memory device may include a plurality of word lines extending along a direction crossing a plurality of active regions and at least one source line connected to a plurality of first active regions arranged on a level that is lower than the upper surface of a substrate. A plurality of contact pads may be connected to a plurality of second active regions and a plurality of buried contact plugs may be connected to the plurality of second active regions via the plurality of contact pads. Said buried contact pads may further be arranged in a hexagonal array structure. A plurality of variable resistance structures may be connected to the plurality of second active regions and arranged in a hexagonal array structure.Type: ApplicationFiled: July 22, 2014Publication date: March 5, 2015Inventors: Yong-kwan KIM, Dae-eun JEONG, Shin-hee HAN
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Patent number: 8203135Abstract: A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another.Type: GrantFiled: February 1, 2010Date of Patent: June 19, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-Rie Sim, Jung-Hoon Park, Yoon-Jong Song, Jae-Min Shin, Shin-Hee Han
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Publication number: 20100200833Abstract: A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another.Type: ApplicationFiled: February 1, 2010Publication date: August 12, 2010Inventors: Kyu-Rie SIM, Jung-Hoon PARK, Yoon-Jong SONG, Jae-Min SHIN, Shin-Hee HAN