Patents by Inventor Shin-Hwan Kang
Shin-Hwan Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230292515Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.Type: ApplicationFiled: May 22, 2023Publication date: September 14, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hwan SON, Kohji KANAMORI, Shin-Hwan KANG, Young Jin KWON
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Patent number: 11696442Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.Type: GrantFiled: August 12, 2020Date of Patent: July 4, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hwan Son, Kohji Kanamori, Shin-Hwan Kang, Young Jin Kwon
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Patent number: 11631692Abstract: A semiconductor memory device includes a peripheral logic structure including peripheral circuits on a substrate, a horizontal semiconductor layer extending along a top surface of the peripheral logic structure, a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction, and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction, which is different from the first direction, wherein each of the plurality of stack structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond the second electrode pad by a first width, and the first electrode pad protrudes in the second direction beyond the second electrode pad by a second width, which is different from the first width.Type: GrantFiled: July 22, 2020Date of Patent: April 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hae Min Lee, Shin Hwan Kang, Jee Hoon Han
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Publication number: 20220254808Abstract: A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Kohji KANAMORI, Min-Yeong SONG, Shin-Hwan KANG
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Patent number: 11335697Abstract: A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.Type: GrantFiled: March 16, 2020Date of Patent: May 17, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Kohji Kanamori, Min-Yeong Song, Shin-Hwan Kang
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Publication number: 20220028740Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.Type: ApplicationFiled: October 13, 2021Publication date: January 27, 2022Inventors: Shin-Hwan KANG, SUN-IL SHIM, SEUNG HYUN
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Patent number: 11171151Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.Type: GrantFiled: March 15, 2019Date of Patent: November 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shin-Hwan Kang, Sun-Il Shim, Seung Hyun
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Patent number: 11004865Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.Type: GrantFiled: November 22, 2019Date of Patent: May 11, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori
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Publication number: 20210036013Abstract: A semiconductor memory device includes a peripheral logic structure including peripheral circuits on a substrate, a horizontal semiconductor layer extending along a top surface of the peripheral logic structure, a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction, and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction, which is different from the first direction, wherein each of the plurality of stack structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond the second electrode pad by a first width, and the first electrode pad protrudes in the second direction beyond the second electrode pad by a second width, which is different from the first width.Type: ApplicationFiled: July 22, 2020Publication date: February 4, 2021Inventors: Hae Min LEE, Shin Hwan KANG, Jee Hoon HAN
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Patent number: 10886289Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.Type: GrantFiled: April 5, 2018Date of Patent: January 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Shin-hwan Kang, Young-hwan Son, Dong-seog Eun, Chang-sup Lee, Jae-hoon Jang
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Publication number: 20200411546Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.Type: ApplicationFiled: August 12, 2020Publication date: December 31, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Hwan SON, Kohji KANAMORI, Shin-Hwan KANG, Young Jin KWON
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Patent number: 10847537Abstract: A three-dimensional semiconductor memory device includes: gate electrodes and mold insulation layers alternately stacked on a substrate; a channel layer passing through the gate electrodes and the mold insulation layers; and a gate dielectric layer between the gate electrodes and the channel layer. The gate dielectric layer and the channel layer may be in an upper portion of the substrate and may be bent at a first angle and extend under the mold insulation layers in the upper portion of the substrate.Type: GrantFiled: January 30, 2019Date of Patent: November 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Young Hwan Son, Seo Goo Kang, Shin Hwan Kang
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Patent number: 10748923Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.Type: GrantFiled: December 4, 2018Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hwan Son, Kohji Kanamori, Shin-Hwan Kang, Young Jin Kwon
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Publication number: 20200219898Abstract: A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.Type: ApplicationFiled: March 16, 2020Publication date: July 9, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Kohji KANAMORI, Min-Yeong SONG, Shin-Hwan KANG
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Publication number: 20200091189Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.Type: ApplicationFiled: November 22, 2019Publication date: March 19, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Kwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori
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Publication number: 20200043943Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.Type: ApplicationFiled: March 15, 2019Publication date: February 6, 2020Inventors: Shin-Hwan KANG, SUN-IL SHIM, SEUNG HYUN
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Publication number: 20200027894Abstract: A three-dimensional semiconductor memory device includes: gate electrodes and mold insulation layers alternately stacked on a substrate; a channel layer passing through the gate electrodes and the mold insulation layers; and a gate dielectric layer between the gate electrodes and the channel layer. The gate dielectric layer and the channel layer may be in an upper portion of the substrate and may be bent at a first angle and extend under the mold insulation layers in the upper portion of the substrate.Type: ApplicationFiled: January 30, 2019Publication date: January 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Young Hwan SON, Seo Goo KANG, Shin Hwan KANG
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Patent number: 10522562Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.Type: GrantFiled: October 2, 2018Date of Patent: December 31, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori
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Publication number: 20190326316Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.Type: ApplicationFiled: December 4, 2018Publication date: October 24, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: YOUNG-HWAN SON, Kohji Kanamori, Shin-Hwan Kang, Young Jin Kwon
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Patent number: 10453859Abstract: A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.Type: GrantFiled: August 30, 2018Date of Patent: October 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kohji Kanamori, Shin-Hwan Kang, Young-Woo Park, Jung-Hoon Park