Patents by Inventor Shin-Hye Kim

Shin-Hye Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959003
    Abstract: A quantum dot including a core including a semiconductor nanocrystal including a Group III-V compound; and a first semiconductor nanocrystal shell disposed on the semiconductor nanocrystal core, the first semiconductor nanocrystal shell including zinc, selenium, and optionally sulfur, and a second semiconductor nanocrystal shell disposed on the first semiconductor nanocrystal shell, the second semiconductor nanocrystal shell including zinc, sulfur, and optionally selenium, wherein the quantum dot does not include cadmium, an emission peak wavelength of the quantum dot is in a range of about 500 nanometers (nm) to about 550 nm, and an ultraviolet-visible absorption spectrum of the quantum dot includes a first exciton absorption peak and a second exciton absorption peak, a composition including the same, a composite, and an electronic device.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD
    Inventors: Nayoun Won, Garam Park, Shin Ae Jun, Tae Gon Kim, Taekhoon Kim, Shang Hyeun Park, Mi Hye Lim
  • Patent number: 10686069
    Abstract: A semiconductor device includes a substrate and a plurality of semiconductor fins protruding from the substrate. Source/drain regions are disposed at tops of respective ones of the semiconductor fins, each having a width greater than a width of individual ones of the semiconductor fins. A gate electrode is disposed on side surfaces of the semiconductor fins below the source/drain regions. Insulating layers contact the side surfaces of the semiconductor fins and cover upper surfaces of the gate electrode.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shin Hye Kim, Kyung Seok Oh, Gu Young Cho, Sang Jin Hyun
  • Publication number: 20190157452
    Abstract: A semiconductor device includes a substrate and a plurality of semiconductor fins protruding from the substrate. Source/drain regions are disposed at tops of respective ones of the semiconductor fins, each having a width greater than a width of individual ones of the semiconductor fins. A gate electrode is disposed on side surfaces of the semiconductor fins below the source/drain regions. Insulating layers contact the side surfaces of the semiconductor fins and cover upper surfaces of the gate electrode.
    Type: Application
    Filed: July 5, 2018
    Publication date: May 23, 2019
    Inventors: Shin Hye Kim, Kyung Seok Oh, Gu Young Cho, Sang Jin Hyun
  • Patent number: 8697583
    Abstract: Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-seok Oh, Kyung-mun Byun, Shin-hye Kim, Deok-young Jung, Gil-heyun Choi, Eunkee Hong
  • Patent number: 8624354
    Abstract: A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-hye Kim, Kyung-mun Byun, Hong-rae Kim, Gil-heyun Choi, Eun-kee Hong
  • Patent number: 8252655
    Abstract: In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun-Hee Bai, Chul-Ho Shin, Shin-Hye Kim, Sang-Kuk Kim
  • Publication number: 20120058647
    Abstract: Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 8, 2012
    Inventors: Kyung-seok Oh, Kyung-mun Byun, Shin-hye Kim, Deok-young Jung, Gil-heyun Choi, Eunkee Hong
  • Publication number: 20110143532
    Abstract: In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern.
    Type: Application
    Filed: May 17, 2010
    Publication date: June 16, 2011
    Inventors: Keun-Hee Bai, Chul-Ho Shin, Shin-Hye Kim, Sang-Kuk Kim
  • Publication number: 20110115051
    Abstract: A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed.
    Type: Application
    Filed: July 2, 2010
    Publication date: May 19, 2011
    Inventors: Shin-hye Kim, Kyung-mun Byun, Hong-rae Kim, Gil-heyun Choi, Eun-kee Hong
  • Patent number: 7777212
    Abstract: Phase change memory devices include a heating electrode on a substrate and a phase change material pattern on the heating electrode. An adhesive pattern is disposed between the heating electrode and the phase change material pattern. The adhesive pattern contains carbon. Methods of fabricating phase change memory devices are also provided.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Geun An, Hideki Horii, Min-Young Park, Shin-Hye Kim
  • Patent number: 7459745
    Abstract: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: December 2, 2008
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Ju-Bum Lee, Shin-Hye Kim
  • Patent number: 7439150
    Abstract: In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: October 21, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-Hye Kim, Ju-Bum Lee, Min Kim
  • Publication number: 20080173858
    Abstract: Phase change memory devices include a heating electrode on a substrate and a phase change material pattern on the heating electrode. An adhesive pattern is disposed between the heating electrode and the phase change material pattern. The adhesive pattern contains carbon. Methods of fabricating phase change memory devices are also provided.
    Type: Application
    Filed: January 10, 2008
    Publication date: July 24, 2008
    Inventors: Hyeong-Geun An, Hideki Horii, Min-Young Park, Shin-Hye Kim
  • Publication number: 20080023745
    Abstract: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures.
    Type: Application
    Filed: October 2, 2007
    Publication date: January 31, 2008
    Inventors: Ju-Bum Lee, Shin-Hye Kim
  • Publication number: 20080026538
    Abstract: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures.
    Type: Application
    Filed: October 2, 2007
    Publication date: January 31, 2008
    Inventors: Ju Lee, Shin-Hye Kim
  • Patent number: 7288454
    Abstract: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 30, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Bum Lee, Shin-Hye Kim
  • Publication number: 20070120230
    Abstract: In a layer structure, a method of forming the layer structure, a method of manufacturing a capacitor having the layer structure and a method of manufacturing a semiconductor device having the capacitor, a structure may be formed on a substrate. A first insulation layer including at least one kind of impurities may be formed on the structure. A flatness of the first insulation layer may fluctuate according to the type and concentration of the impurities. The first insulation layer may include silicate glass doped with first impurities including an element in Group III and/or second impurities including an element in Group V. The flatness of the first insulation layer may improve in proportion to the concentration of the first impurities whereas in inverse proportion to the concentration of the second impurities. Accordingly, the flatness of the first insulation layer may be determined by adjusting the type and concentration of the impurities.
    Type: Application
    Filed: October 24, 2006
    Publication date: May 31, 2007
    Inventors: Shin-Hye Kim, Ju-Bum Lee, Do-Hyung Kim
  • Patent number: 7163869
    Abstract: A STI (shallow trench isolation) structure is formed with a liner layer that is converted from an initial material to a subsequent material. For example, the liner layer is initially comprised of nitride during wet etch-back of a dielectric fill material comprised of oxide to protect an oxide layer on a semiconductor substrate. Thereafter, an exposed portion of the liner layer is converted into the subsequent material of oxide to protect the dielectric fill material within the STI opening during etching away of masking layers to prevent formation of dents in the STI structure.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: January 16, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-Hye Kim, Min Kim, Seung-Jae Lee
  • Publication number: 20060073669
    Abstract: In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.
    Type: Application
    Filed: October 5, 2005
    Publication date: April 6, 2006
    Inventors: Shin-Hye Kim, Ju-Bum Lee, Min Kim
  • Patent number: D1012075
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: January 23, 2024
    Assignee: SPIGEN KOREA CO., LTD.
    Inventor: Shin Hye Kim