Patents by Inventor Shinichi Hiramatsu
Shinichi Hiramatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140089540Abstract: A storage apparatus 10 includes a communication control processor 11 that is a processor configured to control communications with a host apparatus 3, and plurality of main processors 12 each configured to perform an I/O process on a storage drive 171 according to an I/O request received from the host apparatus 3. The storage apparatus 10 manages data to be stored or that has been stored in the storage drive 171 in accordance with the CKD format. The storage apparatus 10 distributes the I/O process to the plurality of main processors 12 in units of the data fields on basis of the operation rates of the respective main processors 12, information on a C field, a K field, and a D field that are data fields forming a record of data targeted by the I/O process and managed in CKD format, and an I/O load indicator being a load indicator of the I/O process currently running on each of the main processors.Type: ApplicationFiled: September 25, 2012Publication date: March 27, 2014Inventors: Masaru Tsukada, Shinichi Hiramatsu, Yuya Goto, Jun Miyashita
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Publication number: 20130339647Abstract: The present invention continues host access and holds data of a migration source volume as the latest data even when a fault occurs in any of a plurality of access paths. Upon receiving a first write command from a host computer via a first access path, the migration source controller writes first update data to the migration source volume and, upon receiving a second write command from the host computer via a second access path, the migration destination controller transfers second update data to the migration source controller via a storage path and, upon receiving the second update data from the migration destination controller, the migration source controller writes the second update data to the migration source volume.Type: ApplicationFiled: June 18, 2012Publication date: December 19, 2013Applicant: HITACHI, LTD.Inventors: Kazue Jindo, Hidetoshi Sakaki, Junichi Muto, Shinichi Hiramatsu, Jun Miyashita
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Publication number: 20130159765Abstract: When a double failure occurs in a storage device storing a mutual conversion table such as a track management information table in thin provisioning, the storage address of the track within the storage subsystem cannot be specified and user data is lost. In order to solve the problem, the present invention provides a storage subsystem capable of recovering data by referring to a track address stored in an accessible track management information table or a user data section, renewing the damaged track management information table to restore the corresponding relationship between track management information tables, and enabling the user data to be accessed again.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Applicant: HITACHI, LTD.Inventors: Shinichi Hiramatsu, Kazue Jindo
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Patent number: 8459730Abstract: A roof apparatus includes a functional bracket supporting a movable panel, a guide rail extending in a longitudinal direction of a vehicle, a drive shoe moving along the guide rail, a front link connected to the functional bracket to move in the longitudinal direction in conjunction with the movement of the drive shoe, a front guide portion guiding the functional bracket and the front link in the longitudinal direction, a check member engaged with the drive shoe to move rearward with the drive shoe when a distance of the rearward movement of the drive shoe is shorter than a predetermined distance, the check member disengaged from the drive shoe when the distance of the rearward movement of the drive shoe is equal to or longer than the predetermined distance, a rear link engaged with the check member, and a rear guide portion guiding the rear link in the longitudinal direction.Type: GrantFiled: January 23, 2012Date of Patent: June 11, 2013Assignee: Aisin Seiki Kabushiki KaishaInventors: Kazuki Sawada, Makoto Muranaka, Shinichi Hiramatsu
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Patent number: 8388052Abstract: A deflector apparatus for a vehicle includes the deflector body configured to be provided along a front edge portion of an opening portion formed on a roof portion of a vehicle and to be deployed by projecting above a surface of the roof portion. The deflector body includes a mesh member extending along the front edge portion of the opening portion. The deflector apparatus for the vehicle also includes a pair of resin frames provided at end portions of the mesh member in a widthwise direction of the mesh member respectively to extend in a lengthwise direction of the mesh member over an entire length of the mesh member. The pair of resin frames is resin-molded integrally with the mesh member and covers the end portions of the mesh member including edges of the mesh member in the widthwise direction of the mesh member.Type: GrantFiled: July 21, 2011Date of Patent: March 5, 2013Assignee: Aisin Seiki Kabushiki KaishaInventors: Kazuki Sawada, Yoshitaka Ide, Shinichi Hiramatsu
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Patent number: 8312185Abstract: A storage apparatus 10 includes channel devices (each being CHA_PK 11) and microprocessors (each being MP_PK 12). CHA_PK 11 and MP_PK 12 respectively store therein control information being information designating logical volumes (LDEVs) 171 accessible by respective MP_PKs 12. Upon receipt of an I/O request from a management apparatus 20, CHA_PK 11 transmits, based on the control information stored therein, an I/O command to MP_PK 12 having an access right to a logical volume to which the I/O request is directed. In the storage apparatus 10, MP_PK 12 having received the I/O command from CHA_PK 11 judges based on the control information stored therein whether MP_PK 12 itself has an access right to the logical volume, and transmits the control information therein to CHA_PK 11 when judging that it does not have the access right, whereby the control information in CHA_PK 11 is updated.Type: GrantFiled: May 6, 2011Date of Patent: November 13, 2012Assignee: Hitachi, Ltd.Inventors: Kunihiko Nashimoto, Shinichi Hiramatsu, Noboru Furuumi
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Publication number: 20120193945Abstract: A roof apparatus includes a functional bracket supporting a movable panel, a guide rail extending in a longitudinal direction of a vehicle, a drive shoe moving along the guide rail, a front link connected to the functional bracket to move in the longitudinal direction in conjunction with the movement of the drive shoe, a front guide portion guiding the functional bracket and the front link in the longitudinal direction, a check member engaged with the drive shoe to move rearward with the drive shoe when a distance of the rearward movement of the drive shoe is shorter than a predetermined distance, the check member disengaged from the drive shoe when the distance of the rearward movement of the drive shoe is equal to or longer than the predetermined distance, a rear link engaged with the check member, and a rear guide portion guiding the rear link in the longitudinal direction.Type: ApplicationFiled: January 23, 2012Publication date: August 2, 2012Applicant: AISIN SEIKI KABUSHIKI KAISHAInventors: Kazuki Sawada, Makoto Muranaka, Shinichi Hiramatsu
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Publication number: 20120056449Abstract: A deflector apparatus for a vehicle includes the deflector body configured to be provided along a front edge portion of an opening portion formed on a roof portion of a vehicle and to be deployed by projecting above a surface of the roof portion. The deflector body includes a mesh member extending along the front edge portion of the opening portion. The deflector apparatus for the vehicle also includes a pair of resin frames provided at end portions of the mesh member in a widthwise direction of the mesh member respectively to extend in a lengthwise direction of the mesh member over an entire length of the mesh member. The pair of resin frames is resin-molded integrally with the mesh member and covers the end portions of the mesh member including edges of the mesh member in the widthwise direction of the mesh member.Type: ApplicationFiled: July 21, 2011Publication date: March 8, 2012Inventors: Kazuki Sawada, Yoshitaka Ide, Shinichi Hiramatsu
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Publication number: 20110213904Abstract: A storage apparatus 10 includes channel devices (each being CHA_PK 11) and microprocessors (each being MP_PK 12). CHA_PK 11 and MP_PK 12 respectively store therein control information being information designating logical volumes (LDEVs) 171 accessible by respective MP_PKs 12. Upon receipt of an I/O request from a management apparatus 20, CHA_PK 11 transmits, based on the control information stored therein, an I/O command to MP_PK 12 having an access right to a logical volume to which the I/O request is directed. In the storage apparatus 10, MP_PK 12 having received the I/O command from CHA_PK 11 judges based on the control information stored therein whether MP_PK 12 itself has an access right to the logical volume, and transmits the control information therein to CHA_PK 11 when judging that it does not have the access right, whereby the control information in CHA_PK 11 is updated.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Inventors: Kunihiko Nashimoto, Shinichi Hiramatsu, Noboru Furuumi
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Patent number: 7962671Abstract: A storage apparatus 10 includes channel devices (each being CHA_PK 11) and microprocessors (each being MP_PK 12). CHA_PK 11 and MP_PK 12 respectively store therein control information being information designating logical volumes (LDEVs) 171 accessible by respective MP_PKs 12. Upon receipt of an I/O request from a management apparatus 20, CHA_PK 11 transmits, based on the control information stored therein, an I/O command to MP_PK 12 having an access right to a logical volume to which the I/O request is directed. In the storage apparatus 10, MP_PK 12 having received the I/O command from CHA_PK 11 judges based on the control information stored therein whether MP_PK 12 itself has an access right to the logical volume, and transmits the control information therein to CHA_PK 11 when judging that it does not have the access right, whereby the control information in CHA_PK 11 is updated.Type: GrantFiled: November 21, 2008Date of Patent: June 14, 2011Assignee: Hitachi, Ltd.Inventors: Kunihiko Nashimoto, Shinichi Hiramatsu, Noboru Furuumi
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Patent number: 7899971Abstract: A storage controller of the present invention is capable of providing a plurality of external volumes to a mainframe as a single virtual volume without lowering write performance. A virtual volume inside a main storage apparatus is associated with a plurality of external volumes inside an external storage apparatus. When the mainframe formats the virtual volume, a control information creation unit of the main storage apparatus creates and stores control information related to the virtual volume. Consequently, it is possible to enhance processing performance when the write size specified by the mainframe coincides with the data size set in the write destination, that is, during a so-called isometric write.Type: GrantFiled: March 5, 2008Date of Patent: March 1, 2011Assignee: Hitachi, Ltd.Inventors: Akihiro Mori, Shinichi Hiramatsu
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Patent number: 7831744Abstract: A storage system that includes: a plurality of microprocessors; a plurality of storage areas to be formed to a drive group; an assignment section that assigns, to each of the microprocessors, an ownership of accessing any of the storage areas; a management section that manages, as an operating ratio, a proportion of a time to be taken for each of the microprocessors to execute a request issued to each of the storage areas; a search section that searches, for transferring the ownership assigned to an arbitrary one of the microprocessors to any of the another microprocessor determined based on the operating ratio, one or more of the storage areas under the ownership of the arbitrary microprocessor for a transfer-target storage area; and a transfer section that transfers, to the another microprocessor, the ownership of the transfer-target storage area that is assigned to the arbitrary microprocessor.Type: GrantFiled: August 15, 2008Date of Patent: November 9, 2010Assignee: Hitachi, Ltd.Inventors: Shinichi Hiramatsu, Hisaharu Takeuchi
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Publication number: 20100274929Abstract: A storage apparatus 10 includes channel devices (each being CHA_PK 11) and microprocessors (each being MP_PK 12). CHA_PK 11 and MP_PK 12 respectively store therein control information being information designating logical volumes (LDEVs) 171 accessible by respective MP_PKs 12. Upon receipt of an I/O request from a management apparatus 20, CHA_PK 11 transmits, based on the control information stored therein, an I/O command to MP_PK 12 having an access right to a logical volume to which the I/O request is directed. In the storage apparatus 10, MP_PK 12 having received the I/O command from CHA_PK 11 judges based on the control information stored therein whether MP_PK 12 itself has an access right to the logical volume, and transmits the control information therein to CHA_PK 11 when judging that it does not have the access right, whereby the control information in CHA_PK 11 is updated.Type: ApplicationFiled: November 21, 2008Publication date: October 28, 2010Applicant: HITACHI, LTD.Inventors: Kunihiko Nashimoto, Shinichi Hiramatsu, Noboru Furuumi
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Publication number: 20090307385Abstract: A storage system that includes: a plurality of microprocessors; a plurality of storage areas to be formed to a drive group; an assignment section that assigns, to each of the microprocessors, an ownership of accessing any of the storage areas; a management section that manages, as an operating ratio, a proportion of a time to be taken for each of the microprocessors to execute a request issued to each of the storage areas; a search section that searches, for transferring the ownership assigned to an arbitrary one of the microprocessors to any of the another microprocessor determined based on the operating ratio, one or more of the storage areas under the ownership of the arbitrary microprocessor for a transfer-target storage area; and a transfer section that transfers, to the another microprocessor, the ownership of the transfer-target storage area that is assigned to the arbitrary microprocessor.Type: ApplicationFiled: August 15, 2008Publication date: December 10, 2009Inventors: Shinichi Hiramatsu, Hisaharu Takeuchi
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Patent number: 7617334Abstract: In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and transmits the code to a PORT in the DKC. In the DKC, the PORT decodes the code by the decode program, and a CP sequentially processes each command obtained by the decoding and returns a return code representing the end state of the processing. The host receives the return code to recognize the end state of the processing.Type: GrantFiled: June 20, 2008Date of Patent: November 10, 2009Assignee: Hitachi, Ltd.Inventors: Junichi Muto, Isamu Kurokawa, Shinichi Hiramatsu, Takuya Ichikawa
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Publication number: 20090187730Abstract: A storage controller of the present invention is capable of providing a plurality of external volumes to a mainframe as a single virtual volume without lowering write performance. A virtual volume inside a main storage apparatus is associated with a plurality of external volumes inside an external storage apparatus. When the mainframe formats the virtual volume, a control information creation unit of the main storage apparatus creates and stores control information related to the virtual volume. Consequently, it is possible to enhance processing performance when the write size specified by the mainframe coincides with the data size set in the write destination, that is, during a so-called isometric write.Type: ApplicationFiled: March 5, 2008Publication date: July 23, 2009Inventors: Akihiro Mori, Shinichi Hiramatsu
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Publication number: 20080256264Abstract: In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and transmits the code to a PORT in the DKC. In the DKC, the PORT decodes the code by the decode program, and a CP sequentially processes each command obtained by the decoding and returns a return code representing the end state of the processing. The host receives the return code to recognize the end state of the processing.Type: ApplicationFiled: June 20, 2008Publication date: October 16, 2008Inventors: Junichi Muto, Isamu Kurokawa, Shinichi Hiramatsu, Takuya Ichikawa
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Patent number: 7373465Abstract: In a data processing system in which a host processing apparatus and a storage subsystem are connected via a channel interface, the present invention makes it possible to expand the number of logical device addresses in excess of the device address limitations of the channel interface, and also enhances the performance of parallel access processing for the same logical device. When an access request is generated for a logical device, the host processing apparatus stores the logical device address to be accessed in a prefix command of a channel command word (CCW) for the access request, sets this CCW in a device information block of a frame which complies with the channel interface, sets a parallel access identifier for identifying a plurality of accesses for the same device in a device address of this frame, and then sends this frame to the storage subsystem.Type: GrantFiled: November 8, 2005Date of Patent: May 13, 2008Assignee: Hitachi, Ltd.Inventors: Shinichi Hiramatsu, Isamu Kurokawa, Hisaharu Takeuchi, Jyunichi Muto, Miyuki Yasuda
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Publication number: 20070061463Abstract: In a data processing system in which a host processing apparatus and a storage subsystem are connected via a channel interface, the present invention makes it possible to expand the number of logical device addresses in excess of the device address limitations of the channel interface, and also enhances the performance of parallel access processing for the same logical device. When an access request is generated for a logical device, the host processing apparatus stores the logical device address to be accessed in a prefix command of a channel command word (CCW) for the access request, sets this CCW in a device information block of a frame which complies with the channel interface, sets a parallel access identifier for identifying a plurality of accesses for the same device in a device address of this frame, and then sends this frame to the storage subsystem.Type: ApplicationFiled: November 8, 2005Publication date: March 15, 2007Inventors: Shinichi Hiramatsu, Isamu Kurokawa, Hisaharu Takeuchi, Jyunichi Muto, Miyuki Yasuda
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Publication number: 20060224795Abstract: In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and transmits the code to a PORT in the DKC. In the DKC, the PORT decodes the code by the decode program, and a CP sequentially processes each command obtained by the decoding and returns a return code representing the end state of the processing. The host receives the return code to recognize the end state of the processing.Type: ApplicationFiled: June 2, 2005Publication date: October 5, 2006Inventors: Junichi Muto, Isamu Kurokawa, Shinichi Hiramatsu, Takuya Ichikawa