Abstract: A silicon carbide wafer manufacturing apparatus includes a mounting unit disposed in a reaction chamber. The mounting unit includes a susceptor portion having a mounting surface on which a rear surface of a seed substrate is to be mounted, and a guide portion disposed on the susceptor portion in a state of surrounding the seed substrate. The mounting unit is configured such that a first interval between the seed substrate and the guide portion on an upstream side in a step-flow growth direction is narrower than a second interval between the seed substrate and the guide portion on a downstream side in the step-flow growth direction when an epitaxial layer is grown. The guide portion is configured such that a temperature of the guide portion is lower than a temperature of the seed substrate when the epitaxial layer is grown.

Abstract: A silicon carbide wafer includes a base wafer that is made of silicon carbide and doped with an n-type impurity, and an epitaxial layer that is arranged on a main surface of the base wafer, made of silicon carbide and doped with an n-type impurity. The base wafer has a thickness t1 and an average impurity concentration n1, and the epitaxial layer has a thickness t2 and an average impurity concentration n2. The base wafer and the epitaxial layer are configured so as to satisfy a mathematical formula 1: ?0.0178<0.012+(t2/t1)×0.057-(n2/n1)×0.029-{(t2/t1)-0.273}×{(n2/n1)-0.685}×0.108<0.0178.

Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor element, a first surface-side electrode disposed on a first surface of the semiconductor substrate, and a second surface-side electrode disposed on a second surface of the semiconductor substrate. The semiconductor substrate includes a gallium nitride substrate and first column regions and second column regions disposed on a first principal surface of the gallium nitride substrate and alternately arranged along a c-axis direction in the first principal surface. The first column regions are formed of a first nitride semiconductor layer and the second column regions are formed of a second nitride semiconductor layer that is higher in band gap than the first nitride semiconductor layer. The semiconductor element is configured to enable a current to flow between the first surface and the second surface of the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device includes a trench forming step, a laser irradiation step and a peeling step. In the trench forming step, a trench is formed on a first main surface of a semiconductor substrate having a device structure formed thereon. In the laser irradiation step, a laser is irradiated from a second main surface of the semiconductor substrate to a plane surface that is positioned and extends at a predetermined depth of the semiconductor substrate. In the peeling step, a device layer is peeled off from the semiconductor substrate along the plane surface on which the laser is irradiated. The peeling step may be performed in a state in which the trenches are either unfilled or filled with a material having a lower coefficient of thermal expansion than the semiconductor substrate.

Abstract: A semiconductor chip includes a chip constituent substrate having a first surface and a second surface, and including a layer containing gallium nitride. The chip constituent substrate is provided with a semiconductor element, and components constituting the semiconductor element are located more in an area adjacent to the first surface than in an area adjacent to the second surface. The chip constituent substrate is formed with a through hole penetrating the chip constituent substrate from the first surface to the second surface. The through hole defines a first opening adjacent to the first surface and a second opening adjacent to the second surface, and the first opening is larger than the second opening.

Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.

Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.

Abstract: A semiconductor device has a lateral switching device that includes a channel forming layer, a gate structure portion, a source electrode, a drain electrode, a third semiconductor layer, a fourth semiconductor layer, and a junction gate electrode. The gate structure portion has a gate insulating film provided in a recess portion of the channel forming layer and a MOS gate electrode functioning as a gate electrode of a MOS structure provided on the gate insulating film. The source electrode and the junction gate electrode are coupled through an electrode layer provided on an interlayer insulating film covering the MOS gate electrode. An end of the third semiconductor layer facing the drain electrode protrudes toward the drain electrode from an end of the fourth semiconductor layer facing the drain electrode by a distance in a range of 1 ?m to 5 ?m both inclusive.

Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.

Abstract: A nitride semiconductor device includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. Accordingly, on-resistance is decreased while securing high breakdown voltage.

Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.

Abstract: A semiconductor device has a lateral switching device that includes a channel forming layer, a gate structure portion, a source electrode, a drain electrode, a third semiconductor layer, a fourth semiconductor layer, and a junction gate electrode. The gate structure portion has a gate insulating film provided in a recess portion of the channel forming layer and a MOS gate electrode functioning as a gate electrode of a MOS structure provided on the gate insulating film. The source electrode and the junction gate electrode are coupled through an electrode layer provided on an interlayer insulating film covering the MOS gate electrode. An end of the third semiconductor layer facing the drain electrode protrudes toward the drain electrode from an end of the fourth semiconductor layer facing the drain electrode by a distance in a range of 1 ?m to 5 ?m both inclusive.

Abstract: A semiconductor device includes a GaN device provided with: a substrate made of a semi-insulating material or a semiconductor; a channel-forming layer including a GaN layer arranged on the substrate; a gate structure in which a gate-insulating film in contact with the GaN layer is arranged on the channel-forming layer, the gate structure having a gate electrode arranged across the gate-insulating film; and a source electrode and a drain electrode that are arranged on the channel-forming layer and on opposite sides interposing the gate structure. The donor element concentration at the interface between the gate-insulating film and the GaN layer and at the lattice position on the GaN layer side with respect to the interface is set to be less than or equal to 5.0×1017 cm?3.

Abstract: In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×1011 cm?2 and allows a normally-off element to be reliably provided.

Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.

Abstract: In a semiconductor device, an AlGaN layer includes a first AlGaN layer and a second AlGaN layer. The second AlGaN layer is positioned between a gate structure portion and a drain electrode and is divided into multiple parts in an arrangement direction in which the gate structure portion and the drain electrode are arranged. A second Al mixed crystal ratio of the second AlGaN layer is less than a first Al mixed crystal ratio of the first AlGaN layer. Accordingly, the semiconductor device is a normally-off-type device and is capable of restricting a decrease of a breakdown voltage and an increase of an on-resistance.

Abstract: A nitride semiconductor device includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. Accordingly, on-resistance is decreased while securing high breakdown voltage.

Abstract: In a semiconductor device, an AlGaN layer includes a first AlGaN layer and a second AlGaN layer. The second AlGaN layer is positioned between a gate structure portion and a drain electrode and is divided into multiple parts in an arrangement direction in which the gate structure portion and the drain electrode are arranged. A second Al mixed crystal ratio of the second AlGaN layer is less than a first Al mixed crystal ratio of the first AlGaN layer. Accordingly, the semiconductor device is a normally-off-type device and is capable of restricting a decrease of a breakdown voltage and an increase of an on-resistance.

Abstract: A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode.

Abstract: In a semiconductor device, a gate insulating film is provided with a multi-layer structure including a first insulating film and a second insulating film. The first insulating film is formed of an insulating film containing an element having an oxygen binding force larger than that of an element contained in the second insulating film, and the total charge amount is increased. Specifically, by performing oxygen anneal, it is possible to perform the step of supplying oxygen into an aluminum oxide film and increase the total charge amount. This allows a negative fixed charge density in the gate insulating film in the vicinity of an interface with a GaN layer to be set to a value of not less than 2.5×1011 cm?2 and allows a normally-off element to be reliably provided.