Abstract: A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than twenty (20) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: A multilayer PCB having may include a first sub-composite core having a first core structure sandwiched between a first conductive layer and a second conductive layer, the first core structure including one or more dielectric and conductive layers. A first via hole extends at least partially through the first core structure, wherein an inner surface of the first via hole is plated with a conductive material along a first via segment electrically coupling the first conductive layer to an internal layer or trace within the first core structure. A second via segment extending between the second conductive layer and the internal layer or trace is devoid of the conductive material such that the first via hole is substantially stub free. A first dielectric layer is coupled to the second conductive layer. A second sub-composite core coupled to the first dielectric layer.

Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.

Abstract: A method for making an ultra-thin dielectric printed circuit board (PCB) is provided. A first side of a first conductive layer is removably coupled to a disposable base. A first ultra-thin dielectric layer and a second conductive layer are laminated to a second side of the first conductive layer, where the first ultra-thin dielectric layer is positioned between the first and second conductive layers, and the first ultra-thin dielectric layer is thinner than at least one of the first conductive layer and the second conductive layer. The second conductive layer may then be patterned to form electrical paths. The patterned second conductive layer is then filled with a dielectric filler. One or more conductive layers and one or more ultra-thin dielectric layers may then be coupled to the second conductive layer. The disposable base may then be detached from the first conductive layer.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure.

Abstract: A multilayer PCB having may include a first sub-composite core having a first core structure sandwiched between a first conductive layer and a second conductive layer, the first core structure including one or more dielectric and conductive layers. A first via hole extends at least partially through the first core structure, wherein an inner surface of the first via hole is plated with a conductive material along a first via segment electrically coupling the first conductive layer to an internal layer or trace within the first core structure. A second via segment extending between the second conductive layer and the internal layer or trace is devoid of the conductive material such that the first via hole is substantially stub free. A first dielectric layer is coupled to the second conductive layer. A second sub-composite core coupled to the first dielectric layer.

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.

Abstract: A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than twenty (20) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.

Abstract: Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure.

Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.

Abstract: A core or sub-composite structure is provided including a dielectric layer between a first conductive film and a second conductive film. The first conductive film may include a first peelable/removable cover layer formed on or coupled to a first conductive layer. The second conductive film may include a second peelable/removable cover layer formed on or coupled to a second conductive layer.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.