Patents by Inventor Shinichi Jimbo
Shinichi Jimbo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8053859Abstract: To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region 5 disposed between an n?-type drift layer 3 and a first n-type region 7 above n?-type drift layer 3, facilitates limiting the emitter hole current, preventing latch-up from occurring, raising neither on-resistance nor on-voltage. The semiconductor device according to the invention, which includes a p-type region 4 disposed between the buried insulator region 5 and n?-type drift layer 3, facilitates depleting n?-type drift layer 3 in the OFF-state of the device.Type: GrantFiled: February 28, 2006Date of Patent: November 8, 2011Assignee: Fuji Electric Co., Ltd.Inventors: Hong-fei Lu, Shinichi Jimbo
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Publication number: 20090050932Abstract: To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region 5 disposed between an n?-type drift layer 3 and a first n-type region 7 above n?-type drift layer 3, facilitates limiting the emitter hole current, preventing latch-up from occurring, raising neither on-resistance nor on-voltage. The semiconductor device according to the invention, which includes a p-type region 4 disposed between the buried insulator region 5 and n?-type drift layer 3, facilitates depleting n?-type drift layer 3 in the OFF-state of the device.Type: ApplicationFiled: February 28, 2006Publication date: February 26, 2009Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.Inventors: Hong-fei Lu, Shinichi Jimbo
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Patent number: 7476935Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.Type: GrantFiled: February 10, 2005Date of Patent: January 13, 2009Assignee: Fuji Electric Co., Ltd.Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
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Patent number: 7135751Abstract: A high breakdown voltage junction terminating structure having a loop-like RESURF structure formed on a SOI substrate is disclosed. A lateral IGBT, a lateral FWD, an output stage element and a driving circuit are formed in the inside region of the structure. The lateral IGBT and the lateral FWD are surrounded by a trench isolation region as an insulation region. Drain electrodes of high breakdown voltage NMOSFETs are provided on the inside of the high breakdown voltage junction terminating structure. Along with this, a gate electrode and a source electrode of each of the NMOSFETs are provided on the outside of the high breakdown voltage junction terminating structure. The periphery of the high breakdown voltage junction terminating structure is surrounded by a trench isolation region as a second insulation region. A control circuit is provided on the outside of the second insulation region.Type: GrantFiled: July 21, 2004Date of Patent: November 14, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Shinichi Jimbo, Tatsuhiko Fujihira
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Publication number: 20050145975Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.Type: ApplicationFiled: February 10, 2005Publication date: July 7, 2005Applicant: Fuji Electric Co., Ltd.Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
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Patent number: 6870223Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.Type: GrantFiled: November 21, 2002Date of Patent: March 22, 2005Assignee: Fuji Electric Co., Ltd.Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
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Publication number: 20050056906Abstract: A high breakdown voltage junction terminating structure having a loop-like RESURF structure formed on a SOI substrate is disclosed. A lateral IGBT, a lateral FWD, an output stage element and a driving circuit are formed in the inside region of the structure. The lateral IGBT and the lateral FWD are surrounded by a trench isolation region as an insulation region. Drain electrodes of high breakdown voltage NMOSFETs are provided on the inside of the high breakdown voltage junction terminating structure. Along with this, a gate electrode and a source electrode of each of the NMOSFETs are provided on the outside of the high breakdown voltage junction terminating structure. The periphery of the high breakdown voltage junction terminating structure is surrounded by a trench isolation region as a second insulation region. A control circuit is provided on the outside of the second insulation region.Type: ApplicationFiled: July 21, 2004Publication date: March 17, 2005Inventors: Shinichi Jimbo, Tatsuhiko Fujihira
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Patent number: 6828645Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.Type: GrantFiled: June 12, 2003Date of Patent: December 7, 2004Assignee: Fuji Electric Co., Ltd.Inventors: Shinichi Jimbo, Jun Saito, Tomoyuki Yamazaki
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Publication number: 20030209774Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.Type: ApplicationFiled: June 12, 2003Publication date: November 13, 2003Inventors: Shinichi Jimbo, Jun Saito, Tomoyuki Yamazaki
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Patent number: 6642583Abstract: A semiconductor device is provided having a high voltage driver IC reducing malfunction or device destruction. A high voltage IC chip includes a trench structure that surrounds each of two semiconductor regions at different electrical potentials. Specifically, a first semiconductor region forms a ground-potential-based circuit, and a high voltage junction terminating structure around a second semiconductor region forms a floating-potential-based circuit. A trench structure is formed after digging a trench by implanting a high concentration p+ region on a trench wall, or alternatively, by filling the trench with a p+ doped polysilicon or with a dielectric.Type: GrantFiled: June 11, 2002Date of Patent: November 4, 2003Assignee: Fuji Electric Co., Ltd.Inventors: Shinichi Jimbo, Jun Saito
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Patent number: 6603185Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.Type: GrantFiled: January 31, 2000Date of Patent: August 5, 2003Assignee: Fuji Electric Co., Ltd.Inventors: Shinichi Jimbo, Jun Saito, Tomoyuki Yamazaki
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Publication number: 20030127687Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.Type: ApplicationFiled: November 21, 2002Publication date: July 10, 2003Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
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Publication number: 20020195659Abstract: A semiconductor device is provided having a high voltage driver IC reducing malfunction or device destruction. A high voltage IC chip includes a trench structure that surrounds each of two semiconductor regions at different electrical potentials. Specifically, a first semiconductor region forms a ground-potential-based circuit, and a high voltage junction terminating structure around a second semiconductor region forms a floating-potential-based circuit. A trench structure is formed after digging a trench by implanting a high concentration p+ region on a trench wall, or alternatively, by filling the trench with a p+ doped polysilicon or with a dielectric.Type: ApplicationFiled: June 11, 2002Publication date: December 26, 2002Applicant: FUJI ELECTRIC CO., LTD.Inventors: Shinichi Jimbo, Jun Saito