Patents by Inventor Shinichi Jimbo

Shinichi Jimbo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8053859
    Abstract: To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region 5 disposed between an n?-type drift layer 3 and a first n-type region 7 above n?-type drift layer 3, facilitates limiting the emitter hole current, preventing latch-up from occurring, raising neither on-resistance nor on-voltage. The semiconductor device according to the invention, which includes a p-type region 4 disposed between the buried insulator region 5 and n?-type drift layer 3, facilitates depleting n?-type drift layer 3 in the OFF-state of the device.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: November 8, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hong-fei Lu, Shinichi Jimbo
  • Publication number: 20090050932
    Abstract: To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region 5 disposed between an n?-type drift layer 3 and a first n-type region 7 above n?-type drift layer 3, facilitates limiting the emitter hole current, preventing latch-up from occurring, raising neither on-resistance nor on-voltage. The semiconductor device according to the invention, which includes a p-type region 4 disposed between the buried insulator region 5 and n?-type drift layer 3, facilitates depleting n?-type drift layer 3 in the OFF-state of the device.
    Type: Application
    Filed: February 28, 2006
    Publication date: February 26, 2009
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Hong-fei Lu, Shinichi Jimbo
  • Patent number: 7476935
    Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: January 13, 2009
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
  • Patent number: 7135751
    Abstract: A high breakdown voltage junction terminating structure having a loop-like RESURF structure formed on a SOI substrate is disclosed. A lateral IGBT, a lateral FWD, an output stage element and a driving circuit are formed in the inside region of the structure. The lateral IGBT and the lateral FWD are surrounded by a trench isolation region as an insulation region. Drain electrodes of high breakdown voltage NMOSFETs are provided on the inside of the high breakdown voltage junction terminating structure. Along with this, a gate electrode and a source electrode of each of the NMOSFETs are provided on the outside of the high breakdown voltage junction terminating structure. The periphery of the high breakdown voltage junction terminating structure is surrounded by a trench isolation region as a second insulation region. A control circuit is provided on the outside of the second insulation region.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: November 14, 2006
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Shinichi Jimbo, Tatsuhiko Fujihira
  • Publication number: 20050145975
    Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
    Type: Application
    Filed: February 10, 2005
    Publication date: July 7, 2005
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
  • Patent number: 6870223
    Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: March 22, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
  • Publication number: 20050056906
    Abstract: A high breakdown voltage junction terminating structure having a loop-like RESURF structure formed on a SOI substrate is disclosed. A lateral IGBT, a lateral FWD, an output stage element and a driving circuit are formed in the inside region of the structure. The lateral IGBT and the lateral FWD are surrounded by a trench isolation region as an insulation region. Drain electrodes of high breakdown voltage NMOSFETs are provided on the inside of the high breakdown voltage junction terminating structure. Along with this, a gate electrode and a source electrode of each of the NMOSFETs are provided on the outside of the high breakdown voltage junction terminating structure. The periphery of the high breakdown voltage junction terminating structure is surrounded by a trench isolation region as a second insulation region. A control circuit is provided on the outside of the second insulation region.
    Type: Application
    Filed: July 21, 2004
    Publication date: March 17, 2005
    Inventors: Shinichi Jimbo, Tatsuhiko Fujihira
  • Patent number: 6828645
    Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: December 7, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shinichi Jimbo, Jun Saito, Tomoyuki Yamazaki
  • Publication number: 20030209774
    Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.
    Type: Application
    Filed: June 12, 2003
    Publication date: November 13, 2003
    Inventors: Shinichi Jimbo, Jun Saito, Tomoyuki Yamazaki
  • Patent number: 6642583
    Abstract: A semiconductor device is provided having a high voltage driver IC reducing malfunction or device destruction. A high voltage IC chip includes a trench structure that surrounds each of two semiconductor regions at different electrical potentials. Specifically, a first semiconductor region forms a ground-potential-based circuit, and a high voltage junction terminating structure around a second semiconductor region forms a floating-potential-based circuit. A trench structure is formed after digging a trench by implanting a high concentration p+ region on a trench wall, or alternatively, by filling the trench with a p+ doped polysilicon or with a dielectric.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: November 4, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shinichi Jimbo, Jun Saito
  • Patent number: 6603185
    Abstract: A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: August 5, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Shinichi Jimbo, Jun Saito, Tomoyuki Yamazaki
  • Publication number: 20030127687
    Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
    Type: Application
    Filed: November 21, 2002
    Publication date: July 10, 2003
    Inventors: Naoki Kumagai, Yuuichi Harada, Shinichi Jimbo, Yoshihiro Ikura, Tatsuhiko Fujihira, Kazuhiko Yoshida
  • Publication number: 20020195659
    Abstract: A semiconductor device is provided having a high voltage driver IC reducing malfunction or device destruction. A high voltage IC chip includes a trench structure that surrounds each of two semiconductor regions at different electrical potentials. Specifically, a first semiconductor region forms a ground-potential-based circuit, and a high voltage junction terminating structure around a second semiconductor region forms a floating-potential-based circuit. A trench structure is formed after digging a trench by implanting a high concentration p+ region on a trench wall, or alternatively, by filling the trench with a p+ doped polysilicon or with a dielectric.
    Type: Application
    Filed: June 11, 2002
    Publication date: December 26, 2002
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Shinichi Jimbo, Jun Saito