Patents by Inventor Shinichi Kawaguchi

Shinichi Kawaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6632564
    Abstract: In a non-aqueous electrolyte comprising an organic solvent and a solute dissolved in the organic solvent, a lithium salt containing at least one organic anion selected from phthalimide, a derivative of phthalimide, phthalimidine and a derivative of phthalimidine is used as the solute. Such non-aqueous electrolyte is not liable to react with the negative electrode in a primary battery and a secondary battery during a long-term storage at high temperatures. As a consequence, by using this non-aqueous electrolyte, a non-aqueous electrolyte battery having an excellent storage property can be obtained; and the charge/discharge cycle characteristics are improved in a secondary battery.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: October 14, 2003
    Assignee: Matsushita Electric industrial Co., Ltd.
    Inventors: Tadayoshi Takahashi, Shinichi Kawaguchi, Nobuharu Koshiba
  • Publication number: 20030177318
    Abstract: The present invention, in various embodiments, provides techniques for managing data in a queue. In one embodiment, two write pointers control writing into a memory queue and one read pointer control reading from the queue. Individual entries written into the queue may complete out-of-order and depend on various conditions such as whether the pointer associated with the entries is active or passive, whether the other pointer is tracking a transaction, whether the active pointer is lower, equal to, or higher than the inactive pointer, whether the data is the last piece of data in a transaction, etc. Data read from the queue is in the order of the transaction headers written into the queue. The data may bypass the queue, i.e., the data is not written into the queue, but is loaded directly to an output register.
    Type: Application
    Filed: March 14, 2002
    Publication date: September 18, 2003
    Inventors: Jeanine Picraux, Shinichi Kawaguchi
  • Publication number: 20020174165
    Abstract: In a memory space of a node 101 is mapped an interrupt generating register within an interrupt control circuit 112 provided in a node 102, and by issuing a store command to said memory space, the node 101 transmits said store command to an address of said interrupt generating register via a network 105. An interrupt control circuit 112 receives said store command, generates an interrupt command, and transmits the above interrupt command to a CPU module 109.
    Type: Application
    Filed: May 16, 2002
    Publication date: November 21, 2002
    Applicant: NEC CORPORATION
    Inventor: Shinichi Kawaguchi
  • Publication number: 20020107980
    Abstract: A computer system comprising a plurality of modules that transfer data in packets mutually, whose major feature is that each of the modules comprises an output controlling part for sending out a packet to transmit to the destination via each of a plurality of communication paths, and an input controlling part for receiving packets transmitted from a plurality of communication paths, identifying the identical packets transmitted from different communication paths, and capturing transmit data properly, wherein the input controlling part stores information for use for identifying the captured packets, identifies whether the packet received has already been captured or not, and newly captures a packet if the packet received is yet to be captured, and discards a packet if the packet received has already been captured.
    Type: Application
    Filed: February 4, 2002
    Publication date: August 8, 2002
    Applicant: NEC CORPORATION
    Inventor: Shinichi Kawaguchi
  • Publication number: 20020018460
    Abstract: A network apparatus establishes complete crossbar contact for N basic elements each having the capability to function as one computer. A switch device group having N switch devices is connected to each basic element. Each switch device group is composed of a first switch device that is connected directly to a basic element, a second switch device that is connected to the first switch device, a third switch device that is connected to the second switch device, and so on to a final Nth switch device that is connected to an (N-1)th switch device. The network apparatus includes N loop lines, each loop line connecting one switch device in each switch device group in a loop without duplication. A basic element and a first switch device are bidirectionally connected for input and output of data, and each of the switch devices that make up a switch device group are unidirectionally connected for transferring data in one direction toward the first switch device.
    Type: Application
    Filed: June 26, 2001
    Publication date: February 14, 2002
    Applicant: NEC Corporation
    Inventor: Shinichi Kawaguchi
  • Patent number: D450724
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: November 20, 2001
    Assignee: Kawaguchi Co., Ltd.
    Inventor: Shinichi Kawaguchi