Patents by Inventor Shinichi Kawai
Shinichi Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12116236Abstract: A feeding device includes an accommodation unit that accommodates paper, a feeding tray on which the paper is placed in the accommodation unit and that is controlled so as to be lifted and lowered in a case of being replenished with the paper, and a processor configured to determine a lifting and lowering speed of the feeding tray according to an operation by a user, and perform control such that a lifting and lowering speed of the feeding tray becomes slower than the determined lifting and lowering speed in a case of a state where the determined lifting and lowering speed of the feeding tray is unable to be realized.Type: GrantFiled: November 25, 2021Date of Patent: October 15, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Shinya Harada, Shinichi Kawai, Tomoyasu Tanaka
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Publication number: 20220380156Abstract: A feeding device includes an accommodation unit that accommodates paper, a feeding tray on which the paper is placed in the accommodation unit and that is controlled so as to be lifted and lowered in a case of being replenished with the paper, and a processor configured to determine a lifting and lowering speed of the feeding tray according to an operation by a user, and perform control such that a lifting and lowering speed of the feeding tray becomes slower than the determined lifting and lowering speed in a case of a state where the determined lifting and lowering speed of the feeding tray is unable to be realized.Type: ApplicationFiled: November 25, 2021Publication date: December 1, 2022Applicant: FUJIFILM Business Innovation Corp.Inventors: Shinya HARADA, Shinichi KAWAI, Tomoyasu TANAKA
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Patent number: 11194025Abstract: A solid-state imaging device includes: pixels arranged in a matrix on a semiconductor substrate. Each of the pixels includes: a photoelectric converter that converts received light into a signal charge; at least one read gate that reads the signal charge from the photoelectric converter; charge accumulators that each accumulate the signal charge read by the at least one read gate; and a charge holder that receives, from one of the charge accumulators, transfer of the signal charge accumulated in the charge accumulator, holds the signal charge, and transfers, to one of the charge accumulators, the signal charge held, each of the charge accumulators includes a part of a transfer channel and a part of a transfer electrode overlapping with the part of the transfer channel in a planar view of the semiconductor substrate, and the transfer channel per one pixel comprises transfer channels.Type: GrantFiled: March 12, 2020Date of Patent: December 7, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Sei Suzuki, Junichi Matsuo, Shinichi Kawai
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Publication number: 20200213539Abstract: A solid-state imaging device includes: pixels arranged in a matrix on a semiconductor substrate. Each of the pixels includes: a photoelectric converter that converts received light into a signal charge; at least one read gate that reads the signal charge from the photoelectric converter; charge accumulators that each accumulate the signal charge read by the at least one read gate; and a charge holder that receives, from one of the charge accumulators, transfer of the signal charge accumulated in the charge accumulator, holds the signal charge, and transfers, to one of the charge accumulators, the signal charge held, each of the charge accumulators includes a part of a transfer channel and a part of a transfer electrode overlapping with the part of the transfer channel in a planar view of the semiconductor substrate, and the transfer channel per one pixel comprises transfer channels.Type: ApplicationFiled: March 12, 2020Publication date: July 2, 2020Inventors: Sei SUZUKI, Junichi MATSUO, Shinichi KAWAI
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Patent number: 9503132Abstract: A wireless communication apparatus includes an amplifying unit that amplifies an input signal that includes signals with different frequencies of a first frequency and the second frequency; a measuring unit that measures a level of inter modulation distortion generated in a signal obtained by the input signal being amplified by the amplifying unit; a determining unit that determines whether the level of the inter modulation distortion measured by the measuring unit is equal to or greater than a regulation value that is previously stored; and a control unit that decreases, when a result of the determination obtained by the determining unit indicates that the level of the inter modulation distortion is equal to or greater than the regulation value, a level of a signal input to the amplifying unit.Type: GrantFiled: July 29, 2015Date of Patent: November 22, 2016Assignee: FUJITSU LIMITEDInventors: Mutsuhito Ota, Setsuya Nagaya, Shinichi Kawai, Yusuke Yamamori
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Publication number: 20160080010Abstract: A wireless communication apparatus includes an amplifying unit that amplifies an input signal that includes signals with different frequencies of a first frequency and the second frequency; a measuring unit that measures a level of inter modulation distortion generated in a signal obtained by the input signal being amplified by the amplifying unit; a determining unit that determines whether the level of the inter modulation distortion measured by the measuring unit is equal to or greater than a regulation value that is previously stored; and a control unit that decreases, when a result of the determination obtained by the determining unit indicates that the level of the inter modulation distortion is equal to or greater than the regulation value, a level of a signal input to the amplifying unit.Type: ApplicationFiled: July 29, 2015Publication date: March 17, 2016Inventors: Mutsuhito OTA, Setsuya NAGAYA, Shinichi Kawai, Yusuke Yamamori
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Publication number: 20120099624Abstract: A communication device includes a transmitting circuit that includes a quadrature modulator; a receiving circuit that operates as a quadrature demodulator that, when being in a data non-transferring period, starts when power is switched on and ends when receiving operation starts, switches a local oscillator signal to a harmonic receiving signal, and detects the signal level of a harmonic included in a signal output from the transmitting circuit; a harmonic extracting circuit and a voltage control circuit that extract a harmonic from a modulated signal and adjust the harmonic so as to set the signal level less than or equal to a predetermined threshold. When being in the data non-transferring period, the transmitting circuit outputs a signal to the receiving circuit, the signal being generated by combining an amplified modulated signal with an under-adjustment signal.Type: ApplicationFiled: July 12, 2011Publication date: April 26, 2012Applicant: FUJITSU LIMITEDInventors: Setsuya NAGAYA, Akio Sasaki, Narito Matsuno, Kenji Iwai, Shinichi Kawai
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Patent number: 7791665Abstract: A driving method of a solid-state imaging device including plural high-sensitivity pixels and plural low-sensitivity pixels that are arranged in mixed form in a manner of a two-dimensional array on a semiconductor substrate, the method including driving the solid-state imaging device in such a manner that an exposure period of the low-sensitivity pixels is set shorter than that of the high-sensitivity pixels.Type: GrantFiled: April 16, 2007Date of Patent: September 7, 2010Assignee: Fujifilm CorporationInventor: Shinichi Kawai
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Publication number: 20080169490Abstract: Disclosed is a semiconductor device using an SOI substrate and improving carrier mobility of transistors. Over a thin Si layer formed over a Si substrate through a buried insulating film, a gate electrode is formed through a gate insulating film. On both sides of the gate electrode, S/D layers are formed which penetrate through the Si layer and the buried insulating film into the Si substrate and which have a crystal structure with a lattice constant different from that of the Si substrate or the Si layer. Since a channel region is formed within the Si layer, the short channel effect can be suppressed. In addition, since the S/D layer having a crystal structure different from that of a Si crystal is thickly formed to reach the Si substrate, sufficient stress is generated in the channel region, so that the carrier mobility can be efficiently improved.Type: ApplicationFiled: March 24, 2008Publication date: July 17, 2008Applicant: FUJITSU LIMITEDInventor: Shinichi KAWAI
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Publication number: 20080122007Abstract: A semiconductor device includes a first polycrystalline semiconductor gate electrode structure formed in a first device region of a substrate via a gate insulation film and having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, the first polycrystalline gate electrode structure being doped to the second conductivity type, a second polycrystalline semiconductor gate electrode structure formed in a second device region of the substrate via a gate insulation film and having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, the second polycrystalline gate electrode structure being doped to the first conductivity type, a pair of diffusion regions of the second conductivity type formed in the first device region at respective lateral sides of the first polycrystalline semiconductor gate electrode structure, and a pairType: ApplicationFiled: June 19, 2007Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventors: Shinichi Kawai, Takashi Saiki, Naoyoshi Tamura
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Patent number: 7354817Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.Type: GrantFiled: December 15, 2005Date of Patent: April 8, 2008Assignee: Fujitsu LimitedInventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
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Publication number: 20070242148Abstract: A driving method of a solid-state imaging device including plural high-sensitivity pixels and plural low-sensitivity pixels that are arranged in mixed form in a manner of a two-dimensional array on a semiconductor substrate, the method including driving the solid-state imaging device in such a manner that an exposure period of the low-sensitivity pixels is set shorter than that of the high-sensitivity pixels.Type: ApplicationFiled: April 16, 2007Publication date: October 18, 2007Inventor: Shinichi Kawai
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Patent number: 7157776Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.Type: GrantFiled: February 2, 2006Date of Patent: January 2, 2007Assignee: Fujitsu LimitedInventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
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Publication number: 20060138551Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.Type: ApplicationFiled: February 2, 2006Publication date: June 29, 2006Applicant: Fujitsu LimitedInventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
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Publication number: 20060091473Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.Type: ApplicationFiled: December 15, 2005Publication date: May 4, 2006Applicant: Fujitsu LimitedInventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
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Patent number: 7034366Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.Type: GrantFiled: August 5, 2003Date of Patent: April 25, 2006Assignee: Fujitsu LimitedInventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
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Patent number: 7030626Abstract: A high-frequency oscillation proximity sensor with an improved detection sensitivity uses, as a detection coil 11, a two-thread coil formed of substantively two coil conductors joined together at their first ends to form a joint connection end and twisted together, one of the two coil conductors being used as a resonance circuit coil L1 and the other as a copper resistance compensation coil L2, and comprises a drive circuit 12 for supplying a drive current to the joint connection end of the two-thread coil to thereby drive the detection coil to oscillate, a buffer 13 for taking out an oscillating output voltage generated at the joint connection end of the two-thread coil, and a phase shift circuit 15 for turning the phase of the oscillating output voltage taken out by the buffer by a predetermined angle and feeding it back to the copper resistance compensation coil to thereby negate the copper resistance of the two-thread coil.Type: GrantFiled: June 17, 2002Date of Patent: April 18, 2006Assignee: Yamatake CorporationInventors: Takumi Hayashi, Shinichi Kawai, Hiroshi Hatanaka
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Patent number: 7027192Abstract: When characters are input, the input information is sequentially displayed on a first display, an e-mail address, which is registered in a one-touch key registration area, is retrieved by using the input information, and the retrieved e-mail address is displayed on a second display. Further, when an @ mark is input after a character string input, the information displayed on the second display is switched to a domain name read from the domain name registration area. Thus, the @ mark key, which is always used to input e-mail addresses, is also utilized to switch the display information. Accordingly, the data communication apparatus is capable to prevent the inconvenience of inputting the entire e-mail addresses and to prevent input errors.Type: GrantFiled: September 28, 2001Date of Patent: April 11, 2006Assignee: Panasonic Communications Co., Ltd.Inventor: Shinichi Kawai
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Patent number: 6979856Abstract: A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film. The first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines. The second diffusion region is connected to a program and erase bit line.Type: GrantFiled: August 27, 2003Date of Patent: December 27, 2005Assignee: NEC Electronics CorporationInventors: Teiichiro Nishizaka, Isami Sakai, Akira Yoshino, Shinichi Kawai, Kiyokazu Ishige, Tomohiro Hamajima, Motoko Tanaka
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Patent number: 6977748Abstract: The image communication apparatus of the present invention compares the capacity of data received from a communication line with the capacity of existing memory of the image communication apparatus and determines the presence or absence of any expanded memory in the image communication apparatus when the capacity of the received data exceeds the capacity of the existing memory. Then, when the expanded memory is present, the image communication apparatus compares the capacity of the expanded memory with the capacity of the received data and stores the received data in the expanded memory when the capacity of the expanded memory exceeds the capacity of the received data.Type: GrantFiled: March 23, 2001Date of Patent: December 20, 2005Assignee: Panasonic Communications Co., Ltd.Inventor: Shinichi Kawai