Patents by Inventor Shinichi Kawai

Shinichi Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12116236
    Abstract: A feeding device includes an accommodation unit that accommodates paper, a feeding tray on which the paper is placed in the accommodation unit and that is controlled so as to be lifted and lowered in a case of being replenished with the paper, and a processor configured to determine a lifting and lowering speed of the feeding tray according to an operation by a user, and perform control such that a lifting and lowering speed of the feeding tray becomes slower than the determined lifting and lowering speed in a case of a state where the determined lifting and lowering speed of the feeding tray is unable to be realized.
    Type: Grant
    Filed: November 25, 2021
    Date of Patent: October 15, 2024
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Shinya Harada, Shinichi Kawai, Tomoyasu Tanaka
  • Publication number: 20220380156
    Abstract: A feeding device includes an accommodation unit that accommodates paper, a feeding tray on which the paper is placed in the accommodation unit and that is controlled so as to be lifted and lowered in a case of being replenished with the paper, and a processor configured to determine a lifting and lowering speed of the feeding tray according to an operation by a user, and perform control such that a lifting and lowering speed of the feeding tray becomes slower than the determined lifting and lowering speed in a case of a state where the determined lifting and lowering speed of the feeding tray is unable to be realized.
    Type: Application
    Filed: November 25, 2021
    Publication date: December 1, 2022
    Applicant: FUJIFILM Business Innovation Corp.
    Inventors: Shinya HARADA, Shinichi KAWAI, Tomoyasu TANAKA
  • Patent number: 11194025
    Abstract: A solid-state imaging device includes: pixels arranged in a matrix on a semiconductor substrate. Each of the pixels includes: a photoelectric converter that converts received light into a signal charge; at least one read gate that reads the signal charge from the photoelectric converter; charge accumulators that each accumulate the signal charge read by the at least one read gate; and a charge holder that receives, from one of the charge accumulators, transfer of the signal charge accumulated in the charge accumulator, holds the signal charge, and transfers, to one of the charge accumulators, the signal charge held, each of the charge accumulators includes a part of a transfer channel and a part of a transfer electrode overlapping with the part of the transfer channel in a planar view of the semiconductor substrate, and the transfer channel per one pixel comprises transfer channels.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: December 7, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Sei Suzuki, Junichi Matsuo, Shinichi Kawai
  • Publication number: 20200213539
    Abstract: A solid-state imaging device includes: pixels arranged in a matrix on a semiconductor substrate. Each of the pixels includes: a photoelectric converter that converts received light into a signal charge; at least one read gate that reads the signal charge from the photoelectric converter; charge accumulators that each accumulate the signal charge read by the at least one read gate; and a charge holder that receives, from one of the charge accumulators, transfer of the signal charge accumulated in the charge accumulator, holds the signal charge, and transfers, to one of the charge accumulators, the signal charge held, each of the charge accumulators includes a part of a transfer channel and a part of a transfer electrode overlapping with the part of the transfer channel in a planar view of the semiconductor substrate, and the transfer channel per one pixel comprises transfer channels.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 2, 2020
    Inventors: Sei SUZUKI, Junichi MATSUO, Shinichi KAWAI
  • Patent number: 9503132
    Abstract: A wireless communication apparatus includes an amplifying unit that amplifies an input signal that includes signals with different frequencies of a first frequency and the second frequency; a measuring unit that measures a level of inter modulation distortion generated in a signal obtained by the input signal being amplified by the amplifying unit; a determining unit that determines whether the level of the inter modulation distortion measured by the measuring unit is equal to or greater than a regulation value that is previously stored; and a control unit that decreases, when a result of the determination obtained by the determining unit indicates that the level of the inter modulation distortion is equal to or greater than the regulation value, a level of a signal input to the amplifying unit.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 22, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Mutsuhito Ota, Setsuya Nagaya, Shinichi Kawai, Yusuke Yamamori
  • Publication number: 20160080010
    Abstract: A wireless communication apparatus includes an amplifying unit that amplifies an input signal that includes signals with different frequencies of a first frequency and the second frequency; a measuring unit that measures a level of inter modulation distortion generated in a signal obtained by the input signal being amplified by the amplifying unit; a determining unit that determines whether the level of the inter modulation distortion measured by the measuring unit is equal to or greater than a regulation value that is previously stored; and a control unit that decreases, when a result of the determination obtained by the determining unit indicates that the level of the inter modulation distortion is equal to or greater than the regulation value, a level of a signal input to the amplifying unit.
    Type: Application
    Filed: July 29, 2015
    Publication date: March 17, 2016
    Inventors: Mutsuhito OTA, Setsuya NAGAYA, Shinichi Kawai, Yusuke Yamamori
  • Publication number: 20120099624
    Abstract: A communication device includes a transmitting circuit that includes a quadrature modulator; a receiving circuit that operates as a quadrature demodulator that, when being in a data non-transferring period, starts when power is switched on and ends when receiving operation starts, switches a local oscillator signal to a harmonic receiving signal, and detects the signal level of a harmonic included in a signal output from the transmitting circuit; a harmonic extracting circuit and a voltage control circuit that extract a harmonic from a modulated signal and adjust the harmonic so as to set the signal level less than or equal to a predetermined threshold. When being in the data non-transferring period, the transmitting circuit outputs a signal to the receiving circuit, the signal being generated by combining an amplified modulated signal with an under-adjustment signal.
    Type: Application
    Filed: July 12, 2011
    Publication date: April 26, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Setsuya NAGAYA, Akio Sasaki, Narito Matsuno, Kenji Iwai, Shinichi Kawai
  • Patent number: 7791665
    Abstract: A driving method of a solid-state imaging device including plural high-sensitivity pixels and plural low-sensitivity pixels that are arranged in mixed form in a manner of a two-dimensional array on a semiconductor substrate, the method including driving the solid-state imaging device in such a manner that an exposure period of the low-sensitivity pixels is set shorter than that of the high-sensitivity pixels.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: September 7, 2010
    Assignee: Fujifilm Corporation
    Inventor: Shinichi Kawai
  • Publication number: 20080169490
    Abstract: Disclosed is a semiconductor device using an SOI substrate and improving carrier mobility of transistors. Over a thin Si layer formed over a Si substrate through a buried insulating film, a gate electrode is formed through a gate insulating film. On both sides of the gate electrode, S/D layers are formed which penetrate through the Si layer and the buried insulating film into the Si substrate and which have a crystal structure with a lattice constant different from that of the Si substrate or the Si layer. Since a channel region is formed within the Si layer, the short channel effect can be suppressed. In addition, since the S/D layer having a crystal structure different from that of a Si crystal is thickly formed to reach the Si substrate, sufficient stress is generated in the channel region, so that the carrier mobility can be efficiently improved.
    Type: Application
    Filed: March 24, 2008
    Publication date: July 17, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Shinichi KAWAI
  • Publication number: 20080122007
    Abstract: A semiconductor device includes a first polycrystalline semiconductor gate electrode structure formed in a first device region of a substrate via a gate insulation film and having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, the first polycrystalline gate electrode structure being doped to the second conductivity type, a second polycrystalline semiconductor gate electrode structure formed in a second device region of the substrate via a gate insulation film and having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, the second polycrystalline gate electrode structure being doped to the first conductivity type, a pair of diffusion regions of the second conductivity type formed in the first device region at respective lateral sides of the first polycrystalline semiconductor gate electrode structure, and a pair
    Type: Application
    Filed: June 19, 2007
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Shinichi Kawai, Takashi Saiki, Naoyoshi Tamura
  • Patent number: 7354817
    Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: April 8, 2008
    Assignee: Fujitsu Limited
    Inventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
  • Publication number: 20070242148
    Abstract: A driving method of a solid-state imaging device including plural high-sensitivity pixels and plural low-sensitivity pixels that are arranged in mixed form in a manner of a two-dimensional array on a semiconductor substrate, the method including driving the solid-state imaging device in such a manner that an exposure period of the low-sensitivity pixels is set shorter than that of the high-sensitivity pixels.
    Type: Application
    Filed: April 16, 2007
    Publication date: October 18, 2007
    Inventor: Shinichi Kawai
  • Patent number: 7157776
    Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: January 2, 2007
    Assignee: Fujitsu Limited
    Inventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
  • Publication number: 20060138551
    Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.
    Type: Application
    Filed: February 2, 2006
    Publication date: June 29, 2006
    Applicant: Fujitsu Limited
    Inventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
  • Publication number: 20060091473
    Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.
    Type: Application
    Filed: December 15, 2005
    Publication date: May 4, 2006
    Applicant: Fujitsu Limited
    Inventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
  • Patent number: 7034366
    Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: April 25, 2006
    Assignee: Fujitsu Limited
    Inventors: Taketo Watanabe, Toshio Nomura, Shinichi Kawai, Takayuki Kawamata, Shigeo Satoh
  • Patent number: 7030626
    Abstract: A high-frequency oscillation proximity sensor with an improved detection sensitivity uses, as a detection coil 11, a two-thread coil formed of substantively two coil conductors joined together at their first ends to form a joint connection end and twisted together, one of the two coil conductors being used as a resonance circuit coil L1 and the other as a copper resistance compensation coil L2, and comprises a drive circuit 12 for supplying a drive current to the joint connection end of the two-thread coil to thereby drive the detection coil to oscillate, a buffer 13 for taking out an oscillating output voltage generated at the joint connection end of the two-thread coil, and a phase shift circuit 15 for turning the phase of the oscillating output voltage taken out by the buffer by a predetermined angle and feeding it back to the copper resistance compensation coil to thereby negate the copper resistance of the two-thread coil.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: April 18, 2006
    Assignee: Yamatake Corporation
    Inventors: Takumi Hayashi, Shinichi Kawai, Hiroshi Hatanaka
  • Patent number: 7027192
    Abstract: When characters are input, the input information is sequentially displayed on a first display, an e-mail address, which is registered in a one-touch key registration area, is retrieved by using the input information, and the retrieved e-mail address is displayed on a second display. Further, when an @ mark is input after a character string input, the information displayed on the second display is switched to a domain name read from the domain name registration area. Thus, the @ mark key, which is always used to input e-mail addresses, is also utilized to switch the display information. Accordingly, the data communication apparatus is capable to prevent the inconvenience of inputting the entire e-mail addresses and to prevent input errors.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 11, 2006
    Assignee: Panasonic Communications Co., Ltd.
    Inventor: Shinichi Kawai
  • Patent number: 6979856
    Abstract: A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film. The first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines. The second diffusion region is connected to a program and erase bit line.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: December 27, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Teiichiro Nishizaka, Isami Sakai, Akira Yoshino, Shinichi Kawai, Kiyokazu Ishige, Tomohiro Hamajima, Motoko Tanaka
  • Patent number: 6977748
    Abstract: The image communication apparatus of the present invention compares the capacity of data received from a communication line with the capacity of existing memory of the image communication apparatus and determines the presence or absence of any expanded memory in the image communication apparatus when the capacity of the received data exceeds the capacity of the existing memory. Then, when the expanded memory is present, the image communication apparatus compares the capacity of the expanded memory with the capacity of the received data and stores the received data in the expanded memory when the capacity of the expanded memory exceeds the capacity of the received data.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: December 20, 2005
    Assignee: Panasonic Communications Co., Ltd.
    Inventor: Shinichi Kawai