Abstract: A symmetric multiprocessor (SMP) of hierarchical connection realizing an inter-partition shared memory has at the gateway of an inter-node connection switch from each node, a translator for translating an address of an access command for an area shared between partitions, between a real address used in a partition and a shared area address used in common between partitions. Thereby, the address of a local area of each partition is freely set, and cache coherent control of a shared area is conducted at high speed by using a snoop command of the hierarchical connection SMP. Fault containment between partitions is realized by checking conformity between the address of the access command issued from another partition and the shared area configuration. Nodes included in other partitions may be reset from each partition. In addition, the configuration information of the shared area between partitions may be dynamically modified.

Abstract: A computer resource marketing system using LPAR (logical partitioning) technology that divides a computer resource into a plurality of logical partitions, including a lending server with a logical partition control unit 3 that designates at least one logical partition as a lendable partition, a client system that can borrow a logical partition in the lending server and submit processing to the logical partition, a resource database that stores lending conditions and certification information of logical partitions in the lending server, and a management server that searches the resource database based on a borrowing request from a client system, notifies the client system of a logical partition that meets the requirements of the borrowing request, and authorizes the client system to use the logical partition.

Abstract: A cache coherence control system for a multi CPU system having a plurality of CPU nodes, memory nodes and I/O nodes interconnected by a network. Each CPU node control circuit has an access right memory for managing an access right of the node in the unit of an extended node larger than a block size of the internal cache of a CPU. When a memory access is performed, the access right memory is referred to, and if the node has an access right to the extended block including a target block, the block is accessed without cache coherence control at other nodes.

Abstract: A data transfer method realizing a function similar to Unix's FORK by the following operations: allowing a parent process on a server to issue a request for intermission of communication to a process on a client and allowing the process on the client to issue a report of completion of intermission; allowing the parent process to issue, to a child process created on the server and the process on the client, a request for establishment of a new communication line connection between them; and, if the parent process has received data from the process on the client before the establishment of the new connection, coping the data to the child process.

Abstract: A cache memory unit that preferentially stores specific lines into the cache memory, according to the program nature, dynamically changes the priority ranks of lines, and increases the cache memory hit rate, in which: the lines to be accessed by a processor are divided into groups and definitions of the groups are set in a group definition table; policy whereby to store lines belonging to the groups into the cache memory is set in a policy table; and storing lines into the cache memory is executed, according to the group definitions and the policy of storing set in the above tables.

Abstract: A multiprocessor system can reduce a broadcast for cache memory consistency control with memory access from an I/O device. The multiprocessor system is provided with a cache memory identifier or an owner tag, and a block length table for recording a memory write block length of the I/O device. The cache memory identifier has an exclusive copy. The owner tag records that there is no cache memory having an exclusive copy. If there is an exclusive copy during read through the I/O device, a read request is issued to both a cache holding the copy and a memory. If it is recorded that the copy is not present, data are directly read from the memory. Moreover, when a write block length is recorded in the block length table during write, whole blocks are collected to issue a request for invalidation from the cache and the request is directly written to the memory after the invalidation is completed.