Abstract: In a frequency corrector, a counter divides a clock signal CK to be input into a fraction of a natural number larger than one to generate a signal having a clock frequency. The counter corrects the number of clock pulses of the signal having the clock frequency in response to a correction signal to output a first frequency-divided signal. A frequency divider circuit divides the first divided signal to output a unit time signal having another frequency and another frequency-divided signal Db composed of plural frequencies. A correction timing generator decodes the both divided signals to detect a correction timing for the first divided signal, and generates plural correction timing signals different in timing from each other. A correction signal generator generates the correction signal in response to the correction timing signals and correction values to provide the correction signal to the counter.

Abstract: In a frequency corrector, a counter divides a clock signal CK to be input into a fraction of a natural number larger than one to generate a signal having a clock frequency. The counter corrects the number of clock pulses of the signal having the clock frequency in response to a correction signal to output a first frequency-divided signal. A frequency divider circuit divides the first divided signal to output a unit time signal having another frequency and another frequency-divided signal Db composed of plural frequencies. A correction timing generator decodes the both divided signals to detect a correction timing for the first divided signal, and generates plural correction timing signals different in timing from each other. A correction signal generator generates the correction signal in response to the correction timing signals and correction values to provide the correction signal to the counter.

Abstract: A level shift circuit including a first transistor circuit connected between a power supply line and a first node, a second transistor circuit connected between the power supply line and a second node, a first transistor connected between the ground line and the first node, and a second transistor connected between the ground line and the second node. A gate of the first transistor circuit is connected to the second node, and a gate of the second transistor circuit is connected to the first node. An input signal is supplied to a gate of the first transistor and an inverted value of the input signal is supplied to a gate of the second transistor. Additionally, control transistors switch a ratio of inflow current and emission current of the first node or the second node according to a control signal.

Abstract: A level shift circuit whereby a voltage shift amount is large, operation speed is fast, and the power consumption is low. A p-type first transistor is connected between the power supply line and the first node, a p-type second transistor is connected between the power supply line and the second node, and an n-type third transistor is connected between the ground line and the first node, and an n-type fourth transistor is connected between the ground line and the second node. The gate of the first transistor is connected to the second node, and the gate of the second transistor is connected to the first node. An input signal is supplied to the gate of the third transistor and an inverted value of the input signal is supplied to the gate of the fourth transistor. Additionally, this level shift circuit has a plurality of control transistors. The control transistor switches the ratio of the inflow current and emission current of the first node or the second node according to the control signal.

Abstract: A frequency correction circuit for accurately correcting clock signals of an oscillating frequency with a simplified configuration without adjusting an oscillator circuit generating the oscillating frequency. A count adjuster of a time-base counter (TBC) receives a delay control signal and a clock signal. The count adjuster includes an inverter and an AND gate. The inverter is responsive to the delay control signal and develops an output signal, while the AND gate receives the clock signal. During the high level period of the delay control signal, the AND gate sends out the clock signal, from which one clock has been erased, as a clock signal of the initial stage T-type flip-flop of a clock frequency divider, which then produces an output signal, from which deviations have been removed.

Abstract: A frequency correction circuit for accurately correcting clock signals of an oscillating frequency with a simplified configuration without adjusting an oscillator circuit generating the oscillating frequency. A count adjuster of a time-base counter (TBC) receives a delay control signal and a clock signal. The count adjuster includes an inverter and an AND gate. The inverter is responsive to the delay control signal and develops an output signal, while the AND gate receives the clock signal. During the high level period of the delay control signal, the AND gate sends out the clock signal, from which one clock has been erased, as a clock signal of the initial stage T-type flip-flop of a clock frequency divider, which then produces an output signal, from which deviations have been removed.

Abstract: A data transfer circuit has a control circuit which outputs a clock control signal and a data control signal and receives a selectively controlled write signal and a fixed voltage level corresponding to a mode instruction signal-. An AND gate acts as a first transfer circuit which transfers the clock signal to a holding circuit corresponding to the clock control signal, and a second transfer circuit transfers a data signal to the holding circuit.

Abstract: A phase-locked loop ciruit having two requency dividing circuits which are reset in response to reset signals. The reset signals are produced by second and third frequency divided signal generated by combining the divided frequency of a reference clock signal and an output signal from a voltage controlled oscillator. The phase-locked loop ciruit adjusts rapidly the frquency and the phase of the output signal of the voltage controlled oscillator to correspond to that of the reference clock signal.

Abstract: A level shift circuit whereby a voltage shift amount is large, operation speed is fast, and the power consumption is low. A p-type first transistor is connected between the power supply line and the first node, a p-type second transistor is connected between the power supply line and the second node, and an n-type third transistor is connected between the ground line and the first node, and an n-type fourth transistor is connected between the ground line and the second node. The gate of the first transistor is connected to the second node, and the gate of the second transistor is connected to the first node. An input signal is supplied to the gate of the third transistor and an inverted value of the input signal is supplied to the gate of the fourth transistor. Additionally, this level shift circuit has a plurality of control transistors. The control transistor switches the ratio of the inflow current and emission current of the first node or the second node according to the control signal.

Abstract: The phase-locked loop circuit of the present invention has a frequency dividing circuit which is reset in response to a reset signal that is generated based on said first frequency divided signal generated by dividing a frequency of a reference clock signal and an output signal output from a voltage controlled oscillator. The phase-locked loop circuit of the present invention can adjust the frequency and the phase of the output signal of the voltage controlled oscillator to that of the reference clock signal in a short time.

Abstract: A phase-locked loop circuit having a frequency dividing circuit which is reset in response to a reset signal. The reset signal is generated by a first frequency divided signal generated by dividing the frequency of a reference clock signal and an output signal from a voltage controlled oscillator. The phase-locked loop circuit adjusts rapidly the frequency and the phase of the output signal of the voltage controlled oscillator to correspond to that of the reference clock signal.

Abstract: There is provided an input circuit with reduced electrical power consumption, which processes an input signal given thereto for removing the noise components contained therein and regulating the voltage level thereof as well, and then supplies an output signal therefrom to a subsequent semiconductor integrated circuit. The input circuit 101 is made up of the Schmitt buffer 111, a pull-down resistance 113, an N-transistor 115, a P-transistor 121, an N-transistor 122, a P-transistor 131, an N-transistor 132, an exclusive OR gate 141, and a bus driver 151. The Schmitt buffer 111 is a buffer which has two threshold levels i.e. upper and lower thresholds, and changes the level of the output signal OUT depending on whether the voltage of an input signal IN is higher or lower than these two threshold levels.

Abstract: A flexible photovoltaic device comprises a first, insulating and flexible resin layer; a first electrode formed on the first resin layer; a flexible resin type locking member formed having satisfactory adherence and formed along the inner periphery of the transparent electrode; a semiconductor layer formed to cover the first electrode and the locking member for photoelectric conversion; a second electrode formed on the semiconductor layer; and a second insulating and flexible resin layer formed on the second electrode.

Abstract: A manufacturing method of a photovoltaic device, whereby a photovoltaic device of a large area in the laminated structure of a first resin layer with light- transmitting property, a photo-electric converting element consisting of a transparent electrode layer, a thin-film semiconductor layer and a back electrode layer, and a second resin layer in this order is mechanically cut into an optional size, which is followed by a step wherein the first and second resin layers of the cut photovoltaic device of a smaller area are thermally treated or at least one of the transparent electrode layer and back electrode layer at the section is etched and removed. Because of the above treatment for the cut photovoltaic device of a smaller area, an electric short circuit between the transparent electrode layer and back electrode layer at the section is prevented.

Abstract: A flexible photovoltaic device comprises a first transparent, insulating, and flexible resin layer; a transparent electrode formed on the first resin layer; a flexible resin type locking member formed having satisfactory adherence along the inner periphery of the transparent electrode; a semiconductor layer formed to cover the transparent electrode and the locking member for photoelectric conversion; a back electrode formed on the semiconductor layer; and a second insulating and flexible resin layer formed on the back electrode.