Patents by Inventor Shinichi Kurose

Shinichi Kurose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Voltage change reflecting delay calculation method, and voltage change reflecting delay calculation system
    Patent number: 7171641
    Abstract: A method for designing a semiconductor integrated circuit is proposed. The semiconductor integrated circuit includes power supply terminals each formed out of an area bump and signal terminals. Distance from the logic cell or the module to a power supply area bump closest thereto is obtained for the logic cell or the module. Further, a power supply voltage which is estimated to be actually applied to the logic cell or the module is obtained based on the obtained distance and a power supply voltage applied to the power supply area bump. Finally, a delay is calculated based on the estimated power supply voltage.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: January 30, 2007
    Assignee: Fujitsu Limited
    Inventors: Shinichi Kurose, Seiji Goto
  • Method of designing semiconductor integrated circuit with accurate capacitance extraction
    Patent number: 7032207
    Abstract: A semiconductor integrated circuit includes a block having a first border edge on which an external connection terminal is provided and a second border edge on which no external connection terminal is provided, a wiring prohibited area which extends a first distance from the first border edge and in which no wiring line running parallel to the first border edge exists, and a shielding line which is at a second distance from the second border edge and runs parallel to the second border edge.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: April 18, 2006
    Assignee: Fujitsu Limited
    Inventors: Shinichi Kurose, Kenji Kumagai
  • Method of designing semiconductor integrated circuit with accurate capacitance extraction
    Publication number: 20040168144
    Abstract: A semiconductor integrated circuit includes a block having a first border edge on which an external connection terminal is provided and a second border edge on which no external connection terminal is provided, a wiring prohibited area which extends a first distance from the first border edge and in which no wiring line running parallel to the first border edge exists, and a shielding line which is at a second distance from the second border edge and runs parallel to the second border edge.
    Type: Application
    Filed: January 23, 2004
    Publication date: August 26, 2004
    Applicant: Fujitsu Limited
    Inventors: Shinichi Kurose, Kenji Kumagai
  • Voltage change reflecting delay calculation method, and voltage change reflecting delay calculation system
    Publication number: 20030182637
    Abstract: A method for designing a semiconductor integrated circuit is proposed. The semiconductor integrated circuit includes power supply terminals each formed out of an area bump and signal terminals. Distance from the logic cell or the module to a power supply area bump closest thereto is obtained for the logic cell or the module. Further, a power supply voltage which is estimated to be actually applied to the logic cell or the module is obtained based on the obtained distance and a power supply voltage applied to the power supply area bump. Finally, a delay is calculated based on the estimated power supply voltage.
    Type: Application
    Filed: January 17, 2003
    Publication date: September 25, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Shinichi Kurose, Seiji Goto