Patents by Inventor Shinichi Kuwabara
Shinichi Kuwabara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970003Abstract: Provided is a liquid ejection apparatus, liquid ejection method, dispensing apparatus, and compound introduction apparatus capable of inhibiting contamination of a liquid after being ejected. The liquid ejection apparatus has an ejection unit having an ejection part and an ejection energy generation element that ejects a liquid from the ejection part by using a principle of inkjet ejection into an internal space in a storage part capable of storing the ejected liquid. When ejecting the liquid, the ejection unit covers an opening portion of the storage part to thereby screen the internal space in the storage part from an external space.Type: GrantFiled: March 14, 2022Date of Patent: April 30, 2024Assignee: Canon Kabushiki KaishaInventors: Futoshi Hirose, Shinichi Sakurada, Sachiko Yamauchi, Tatsuaki Orihara, Yoshinori Itoh, Nobuyuki Kuwabara, Tsutomu Shiratori
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Patent number: 11756881Abstract: A semiconductor device includes: a first substrate; a multilayer wiring layer formed on the first substrate; a first inductor formed into a meander shape on the multilayer wiring layer in a plan view; and a second inductor formed into a meander shape on the multilayer wiring layer in a plain view, and arranged so as to be close to the first inductor in a plan view and not to overlap with the first inductor. A transformer is configured by the first inductor and the second inductor and, in a plan view, the first inductor and the second inductor extend along a first direction in which one side of the first substrate extends.Type: GrantFiled: April 15, 2021Date of Patent: September 12, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Uchida, Yasutaka Nakashiba, Shinichi Kuwabara
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Patent number: 11562957Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.Type: GrantFiled: March 3, 2021Date of Patent: January 24, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Kuwabara, Yasutaka Nakashiba
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Publication number: 20210366827Abstract: A semiconductor device includes: a first substrate; a multilayer wiring layer formed on the first substrate; a first inductor formed into a meander shape on the multilayer wiring layer in a plan view; and a second inductor formed into a meander shape on the multilayer wiring layer in a plain view, and arranged so as to be close to the first inductor in a plan view and not to overlap with the first inductor. A transformer is configured by the first inductor and the second inductor and, in a plan view, the first inductor and the second inductor extend along a first direction in which one side of the first substrate extends.Type: ApplicationFiled: April 15, 2021Publication date: November 25, 2021Inventors: Shinichi UCHIDA, Yasutaka NAKASHIBA, Shinichi KUWABARA
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Publication number: 20210343641Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.Type: ApplicationFiled: March 3, 2021Publication date: November 4, 2021Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA
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Patent number: 11145597Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.Type: GrantFiled: July 8, 2019Date of Patent: October 12, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Kuwabara, Yasutaka Nakashiba, Teruhiro Kuwajima
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Patent number: 11139240Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.Type: GrantFiled: January 15, 2020Date of Patent: October 5, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Kuwabara, Yasutaka Nakashiba
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Patent number: 11024566Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.Type: GrantFiled: October 15, 2019Date of Patent: June 1, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Uchida, Akio Ono, Shinichi Kuwabara, Yasutaka Nakashiba
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Patent number: 11004830Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.Type: GrantFiled: October 10, 2019Date of Patent: May 11, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida
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Patent number: 10950543Abstract: The semiconductor device includes a first semiconductor substrate, a first wiring layer, a second wiring layer, a second semiconductor substrate, a first conductive portion, and a second conductive portion. The first wiring layer includes a first electrode pad and a first inductor electrically connected with each other. The second wiring layer includes a second inductor and a second electrode pad electrically connected with each other. The first conductive portion is formed in the second semiconductor substrate, the second wiring layer, and the first wiring layer so as to reach the first electrode pad from the back surface of the second semiconductor substrate. The second conductive portion is formed in the second semiconductor substrate and the second wiring layer so as to reach the second electrode pad from the back surface of the second semiconductor substrate. The first inductor and the second inductor are disposed so as to face each other.Type: GrantFiled: May 9, 2019Date of Patent: March 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Kuwabara, Yasutaka Nakashiba
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Patent number: 10818591Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.Type: GrantFiled: April 16, 2018Date of Patent: October 27, 2020Assignee: Renesas Electronics CorporationInventors: Shinichi Uchida, Yasutaka Nakashiba, Tetsuya Iida, Shinichi Kuwabara
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Publication number: 20200243443Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.Type: ApplicationFiled: January 15, 2020Publication date: July 30, 2020Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA
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Patent number: 10720411Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.Type: GrantFiled: February 19, 2019Date of Patent: July 21, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida
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Publication number: 20200168545Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.Type: ApplicationFiled: October 15, 2019Publication date: May 28, 2020Inventors: Shinichi UCHIDA, Akio ONO, Shinichi KUWABARA, Yasutaka NAKASHIBA
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Publication number: 20200161278Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.Type: ApplicationFiled: October 10, 2019Publication date: May 21, 2020Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA, Tetsuya IIDA
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Patent number: 10656442Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.Type: GrantFiled: May 11, 2018Date of Patent: May 19, 2020Assignee: Renesas Electronics CorporationInventors: Tetsuya Iida, Yasutaka Nakashiba, Shinichi Kuwabara
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Publication number: 20200043847Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.Type: ApplicationFiled: July 8, 2019Publication date: February 6, 2020Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA, Teruhiro KUWAJIMA
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Publication number: 20190371727Abstract: The semiconductor device includes a first semiconductor substrate, a first wiring layer, a second wiring layer, a second semiconductor substrate, a first conductive portion, and a second conductive portion. The first wiring layer includes a first electrode pad and a first inductor electrically connected with each other. The second wiring layer includes a second inductor and a second electrode pad electrically connected with each other. The first conductive portion is formed in the second semiconductor substrate, the second wiring layer, and the first wiring layer so as to reach the first electrode pad from the back surface of the second semiconductor substrate. The second conductive portion is formed in the second semiconductor substrate and the second wiring layer so as to reach the second electrode pad from the back surface of the second semiconductor substrate. The first inductor and the second inductor are disposed so as to face each other.Type: ApplicationFiled: May 9, 2019Publication date: December 5, 2019Inventors: Shinichi Kuwabara, Yasutaka Nakashiba
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Patent number: 10418321Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.Type: GrantFiled: April 16, 2018Date of Patent: September 17, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Kuwabara, Tetsuya Iida, Yasutaka Nakashiba
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Publication number: 20190273066Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.Type: ApplicationFiled: February 19, 2019Publication date: September 5, 2019Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA, Tetsuya IIDA