Abstract: An HDMI source conversion device according to one aspect of the disclosure includes an HDMI interface, an IP interface, and a converter. The HDMI interface receives a first signal based on the HDMI communication protocol. The IP interface receives address information from a control device via a network based on the Internet protocol, the control device being connected to the network, and the address information indicating the address on the network of an HDMI sink conversion device that is a device different from the control device. The converter converts the first signal based on the HDMI communication protocol into a second signal based on the Internet protocol by adding at least the address information to the first signal received by the HDMI interface. The IP interface transmits the second signal to the HDMI sink conversion device via the network.

Abstract: An HDMI source conversion device according to one aspect of the disclosure includes an HDMI interface, an IP interface, and a converter. The HDMI interface receives a first signal based on the HDMI communication protocol. The IP interface receives address information from a control device via a network based on the Internet protocol, the control device being connected to the network, and the address information indicating the address on the network of an HDMI sink conversion device that is a device different from the control device. The converter converts the first signal based on the HDMI communication protocol into a second signal based on the Internet protocol by adding at least the address information to the first signal received by the HDMI interface. The IP interface transmits the second signal to the HDMI sink conversion device via the network.

Abstract: The present invention provides an apparatus for securely acquiring a circuit configuration information set corresponding to a new cryptosystem without increasing the number of reconfigurable circuits. A content playback apparatus includes an FPGA that is reconfigurable. The content playback apparatus stores a decryption circuit program that shows the structure of a decryption circuit that executes decryption in accordance with a prescribed cryptosystem. The FPGA is reconfigured in accordance with the program to configure the decryption circuit. The playback apparatus acquires, from outside, an encrypted file that has been generated by encrypting a file including a decryption circuit program corresponding to the new cryptosystem in accordance with the prescribed cryptosystem, and decrypts the encrypted file by the decryption circuit.

Abstract: An information processing apparatus includes a reconfigurable unit in which a circuit is reconfigured. A generation unit generates design data for the circuit configured by the reconfigurable unit and reduces the amount of design data to be held by a design data storage unit.

Abstract: The present invention provides an apparatus for securely acquire a circuit configuration information set corresponding to a new cryptosystem without increasing the number of reconfigurable circuits. A content playback apparatus 100 includes an FPGA 122 that is reconfigurable. The content playback apparatus 100 stores a decryption circuit program that shows the structure of a decryption circuit that executes decryption in accordance with a prescribed cryptosystem. The FPGA is reconfigured in accordance with the program to configure the decryption circuit. The playback apparatus 100 acquires, from outside, an encrypted file that has been generated by encrypting a file including a decryption circuit program corresponding to the new cryptosystem in accordance with the prescribed cryptosystem, and decrypts the encrypted file by the decryption circuit.

Abstract: A mapping apparatus maps, on a semiconductor integrated circuit, a circuit function described in a circuit description, the semiconductor integrated circuit having a plurality of reconfigurable cores arranged separately from one another and having a logic reconfiguration function. A first group of register circuits are formed between at least two reconfigurable cores included in the plurality of reconfigurable cores and temporarily hold an output from one of the reconfigurable cores and transferring the output to another one of the reconfigurable cores. The mapping apparatus includes a divider that divides the circuit function into a plurality of circuit function blocks, an eliminator that eliminates a register from between the plurality of circuit function blocks and a synthesis executer that executes logic synthesis on each of the plurality of circuit function blocks from between which the register has been eliminated.

Abstract: A semiconductor integrated circuit (100) according to the present invention includes a plurality of reconfigurable cores (101) arranged separately from each other in a matrix, and a first group of register circuits (102) formed between a first and second reconfigurable cores included in the reconfigurable cores (101). Each of the reconfigurable cores (101) operates synchronously with clock signals and has a logic reconfiguration function, and includes a plurality of logic elements (201) that implements predetermined logic and programmable wiring (202 and 203) that interconnects the plurality of logic elements (201). The first group of register circuits (102) temporarily holds output from the first reconfigurable core and transfers the output to the second reconfigurable core.

Abstract: A semiconductor integrated circuit (100) according to the present invention includes a plurality of reconfigurable cores (101) arranged separately from each other in a matrix, and a first group of register circuits (102) formed between a first and second reconfigurable cores included in the reconfigurable cores (101). Each of the reconfigurable cores (101) operates synchronously with clock signals and has a logic reconfiguration function, and includes a plurality of logic elements (201) that implements predetermined logic and programmable wiring (202 and 203) that interconnects the plurality of logic elements (201). The first group of register circuits (102) temporarily holds output from the first reconfigurable core and transfers the output to the second reconfigurable core.

Abstract: A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.

Abstract: An information processing apparatus is provided with a reconfigurable unit (101) in which a circuit can be reconfigured. The provision of a generation unit (103) enables the generation of design data of a circuit configured by the reconfigurable unit (101), and enables a reduction in the amount of design data to be held by a design data storage unit (102).

Abstract: A design data storage unit stores a plurality of pieces of design data. A judgment unit 203 judges whether a circuit for decrypting an encrypted content received from a content server 10 is realized in a reconfigurable unit 208, and judges whether a piece of the design data for realizing the circuit for decrypting the encrypted content is held. If the desired circuit is not realized in the reconfigurable unit 208 and the desired piece of the design data is not held, the desired piece of the design data is acquired from a design data server 30 via a network.

Abstract: The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced. In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.

Abstract: The present invention provides an apparatus for securely acquiring a circuit configuration information set corresponding to a new cryptosystem without increasing the number of reconfigurable circuits. A content playback apparatus 100 includes an FPGA 122 that is reconfigurable. The content playback apparatus 100 stores a decryption circuit program that shows the structure of a decryption circuit that executes decryption in accordance with a prescribed cryptosystem. The FPGA is reconfigured in accordance with the program to configure the decryption circuit. The playback apparatus 100 acquires, from outside, an encrypted file that has been generated by encrypting a file including a decryption circuit program corresponding to the new cryptosystem in accordance with the prescribed cryptosystem, and decrypts the encrypted file by the decryption circuit.

Abstract: A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.

Abstract: The power consumption and area of a programmable logic device formed from programmable logical elements can be reduced. In a programmable logic device 101 formed from programmable logical elements, there are provided first logical elements 102 and second logical elements 104 having the same logic as the first logical elements 102 but having an upper limit of operating speed designed to be lower than that of the first logical elements 102.

Abstract: A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.

Abstract: In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142, respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142, respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

Abstract: In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142, respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142, respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

Abstract: Each of processors has an input/output port provided with a data terminal for transmitting and receiving address information and data to be transferred, a mode terminal for transmitting and receiving a mode signal indicative of whether a signal at the data terminal represents the address information or the data to be transmitted, a read/write terminal for transmitting and receiving a read/write signal indicative of a timing for each of the signal at the data terminal and a signal at the mode terminal, an input buffer and an output buffer each connected to the data terminal, a data memory pointer connected to the internal data memory, and a control circuit connected to the mode terminal and to the read/write terminal.

Abstract: Each of processors has an input/output port provided with a data terminal for transmitting and receiving address information and data to be transferred, a mode terminal for transmitting and receiving a mode signal indicative of whether a signal at the data terminal represents the address information or the data to be transmitted, a read/write terminal for transmitting and receiving a read/write signal indicative of a timing for each of the signal at the data terminal and a signal at the mode terminal, an input buffer and an output buffer each connected to the data terminal, a data memory pointer connected to the internal data memory, and a control circuit connected to the mode terminal and to the read/write terminal.