Patents by Inventor Shinichi Miyatake
Shinichi Miyatake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10276253Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.Type: GrantFiled: August 4, 2017Date of Patent: April 30, 2019Assignee: Micron Technology, Inc.Inventor: Shinichi Miyatake
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Publication number: 20190088654Abstract: Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.Type: ApplicationFiled: November 20, 2018Publication date: March 21, 2019Inventor: Shinichi Miyatake
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Patent number: 10236040Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.Type: GrantFiled: November 15, 2016Date of Patent: March 19, 2019Assignee: Micron Technology, Inc.Inventor: Shinichi Miyatake
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Publication number: 20190043597Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.Type: ApplicationFiled: August 4, 2017Publication date: February 7, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Shinichi Miyatake
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Patent number: 10163906Abstract: Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.Type: GrantFiled: October 14, 2016Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventor: Shinichi Miyatake
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Publication number: 20180137899Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.Type: ApplicationFiled: November 15, 2016Publication date: May 17, 2018Inventor: Shinichi Miyatake
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Publication number: 20180108398Abstract: Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Inventor: Shinichi Miyatake
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Patent number: 9330794Abstract: Apparatuses and methods for programming and reading from anti-fuse cells are disclosed herein. For example, a semiconductor device may include a plurality of word lines, a plurality of bit lines, a cell plate, a plurality of cells, and a control circuit. Each of the plurality of cells includes a switch and a capacitor coupled in series between an associated one of the plurality of bit lines and the cell plate, and the switch is controlled by an associated one of the plurality of word lines. The control circuit is configured to provide the cell plate with a first voltage and further configured to change the cell plate from the first voltage to a second voltage before one of the plurality of word lines is activated.Type: GrantFiled: March 4, 2015Date of Patent: May 3, 2016Assignee: Micron Technology, Inc.Inventor: Shinichi Miyatake
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Patent number: 9081402Abstract: A method for controlling power supply current in a CMOS circuit, the method including applying a first predetermined voltage to a diode connected n-channel replica transistor, the n-channel replica transistor operating in weak inversion, applying a first substrate voltage to the substrate of the n-channel replica transistor so that the current flowing in the n-channel replica transistor equals a first predetermined target current, and applying the first substrate voltage to substrates of n-channel transistors in the CMOS circuit.Type: GrantFiled: June 20, 2014Date of Patent: July 14, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Shinichi Miyatake, Seiji Narui, Hitoshi Tanaka
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Patent number: 9053760Abstract: A semiconductor device including a sense amplifier that includes a first transistor and a second transistor. The first transistor includes a first gate electrode formed over a first channel region and connected to a first bit line, a first diffusion region connected to a second bit line with a first side edge defining the first channel region, and a second diffusion region connected to a power line and includes a second side edge defining the first channel region. The second transistor includes a second gate electrode formed over a second channel region and connected to the second bit line, a third diffusion region connected to the first bit line and includes a third side edge defining the second channel region, and a fourth diffusion region connected to the power line with a fourth side edge defining the second channel region. Directions of the bit lines and diffusion side edges are prescribed.Type: GrantFiled: July 10, 2013Date of Patent: June 9, 2015Assignee: PS4 Luxco S.a.r.l.Inventor: Shinichi Miyatake
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Publication number: 20140300408Abstract: A method for controlling power supply current in a CMOS circuit, the method including applying a first predetermined voltage to a diode connected n-channel replica transistor, the n-channel replica transistor operating in weak inversion, applying a first substrate voltage to the substrate of the n-channel replica transistor so that the current flowing in the n-channel replica transistor equals a first predetermined target current, and applying the first substrate voltage to substrates of n-channel transistors in the CMOS circuitType: ApplicationFiled: June 20, 2014Publication date: October 9, 2014Inventors: Shinichi Miyatake, Seiji Narui, Hitoshi Tanaka
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Patent number: 8773195Abstract: A semiconductor device prevents the ON current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a buffer circuit that generates a power-supply voltage of a CMOS; a first replica transistor that is a replica of a p-channel MOS transistor forming the CMOS, and is diode-connected; a second replica transistor that is a replica of an n-channel MOS transistor forming the CMOS, and is diode-connected; and a voltage controller that controls the voltage between the anode and cathode of the replica transistors so that the current value of the current flowing into the replica transistor becomes equal to a given target value. In this semiconductor device, the buffer circuit generates the power-supply voltage, with the target voltage being a voltage that is controlled by the voltage controller.Type: GrantFiled: March 29, 2010Date of Patent: July 8, 2014Inventors: Shinichi Miyatake, Seiji Narui, Hitoshi Tanaka
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Publication number: 20140022857Abstract: A semiconductor device including a sense amplifier that includes a first transistor and a second transistor. The first transistor includes a first gate electrode formed over a first channel region and connected to a first bit line, a first diffusion region connected to a second bit line with a first side edge defining the first channel region, and a second diffusion region connected to a power line and includes a second side edge defining the first channel region. The second transistor includes a second gate electrode formed over a second channel region and connected to the second bit line, a third diffusion region connected to the first bit line and includes a third side edge defining the second channel region, and a fourth diffusion region connected to the power line with a fourth side edge defining the second channel region. Directions of the bit lines and diffusion side edges are prescribed.Type: ApplicationFiled: July 10, 2013Publication date: January 23, 2014Applicant: Elpida Memory, Inc.Inventor: Shinichi MIYATAKE
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Patent number: 8339868Abstract: To include a memory cell array that stores therein data in a reversible manner, an antifuse circuit that stores therein data in a nonvolatile manner, a sense amplifier array that temporarily holds data that is read from the memory cell array of data to be written in the memory cell array, and a control circuit that performs a control for writing the data held in the sense amplifier array in the antifuse circuit. According to the present invention, it is not required to provide any dedicated latch circuit for each antifuse element. Therefore, a writing process of writing data in the antifuse circuit can be performed at high speed without causing an increase of the chip dimension due to a dedicated latch circuit.Type: GrantFiled: March 18, 2010Date of Patent: December 25, 2012Assignee: Elpida Memory, Inc.Inventor: Shinichi Miyatake
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Patent number: 8222952Abstract: A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value.Type: GrantFiled: March 29, 2010Date of Patent: July 17, 2012Assignee: Elpida Memory, Inc.Inventors: Shinichi Miyatake, Seiji Narui, Hitoshi Tanaka
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Patent number: 8217712Abstract: To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.Type: GrantFiled: December 24, 2009Date of Patent: July 10, 2012Assignee: Elpida Memory, Inc.Inventors: Shinichi Miyatake, Seiji Narui, Hitoshi Tanaka
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Patent number: 7995405Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.Type: GrantFiled: December 14, 2010Date of Patent: August 9, 2011Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Hiroaki Nakaya, Shinichi Miyatake, Yuko Watanabe
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Patent number: 7969765Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.Type: GrantFiled: October 8, 2008Date of Patent: June 28, 2011Assignee: Elpida Memory, Inc.Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
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Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit
Patent number: 7952950Abstract: An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.Type: GrantFiled: October 22, 2008Date of Patent: May 31, 2011Assignee: Elpida Memory, Inc.Inventors: Shinichi Miyatake, Sumio Ogawa -
Publication number: 20110079858Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.Type: ApplicationFiled: December 14, 2010Publication date: April 7, 2011Inventors: Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Hiroaki Nakaya, Shinichi Miyatake, Yuko Watanabe