Abstract: A method of erasing data of a nonvolatile semiconductor memory unit includes the first step of collectively applying a preliminary write pulse to memory transistors, the second step of repeating, up to a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse, the third step of repeating, up to a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse, the fourth step of repeating, up to a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse and the fifth step of repeating a selective recovery operation on t

Abstract: A method of erasing data of a nonvolatile semiconductor memory unit includes the first step of collectively applying a preliminary write pulse to memory transistors, the second step of repeating, up to a first erased state, an operation of collective application of a first erase pulse to the memory transistors with change of intensity of the first erase pulse in second and subsequent application operations of the first erase pulse, the third step of repeating, up to a recovered state, an operation of collective application of a write pulse to the memory transistors with change of intensity of the write pulse in second and subsequent application operations of the write pulse, the fourth step of repeating, up to a second erased state, an operation of collective application of a second erase pulse to the memory transistors with change of intensity of the second erase pulse in second and subsequent application operations of the second erase pulse and the fifth step of repeating a selective recovery operation on t

Abstract: A semiconductor storage device is equipped with flash memories each flash memory has a limited size of spare storage area for rewriting data when a write error occurs, and the storage device calculates the remaining size of the spare storage area after the completion of the re-writing, and examines whether or not the remaining size is smaller than a predetermined value, and generates a warning when the remaining size is smaller than the predetermined value, to thereby acknowledge that the life of each flash memory comes close to the end before completely used up.

Abstract: A semiconductor storage device is equipped with flash memories each flash memory has a limited size of spare storage area for rewriting data when a write error occurs, and the storage device calculates the remaining size of the spare storage area after the completion of the re-writing, and examines whether or not the remaining size is smaller than a predetermined value, and generates a warning when the remaining size is smaller than the predetermined value, to thereby acknowledge that the life of each flash memory comes close to the end before completely used up.

Abstract: A semiconductor storage device for reducing data transmission overhead and thereby reducing a drop in the data transmission rate is provided, together with a data management method therefor. A memory unit for sending data in cluster units is achieved with AND-type flash memory, and data transfers between the memory unit and a buffer unit used as cache memory are accomplished in cluster units.

Abstract: A voltage generating circuit according to the present invention includes an external power supply interconnection supplied with an external power supply voltage, an internal power supply interconnection to supply an internal power supply voltage to a load, a regulator circuit which receives the output of the external power supply interconnection and generates a rated voltage for the internal power supply voltage, a voltage switch transistor to connect the external power supply interconnection and the internal power supply interconnection. The regulator circuit and voltage switch transistor are complementarily activated based on the voltage level of a control node. The voltage generating circuit further includes a voltage switch circuit to switch the voltage level of the control node based on the voltage level of the external power supply interconnection.