Patents by Inventor Shinichi Nakabayashi

Shinichi Nakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7977234
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Publication number: 20100227474
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Application
    Filed: May 18, 2010
    Publication date: September 9, 2010
    Inventors: Toshiyuki ARAI, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 7718526
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: May 18, 2010
    Assignee: Renesas Technology Corporation
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Publication number: 20070259522
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Application
    Filed: July 16, 2007
    Publication date: November 8, 2007
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 7250365
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: July 31, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 6979649
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the water, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edges of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: December 27, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Publication number: 20050250331
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Application
    Filed: June 28, 2005
    Publication date: November 10, 2005
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Publication number: 20030157768
    Abstract: Disclosed is a method to achieve the planarization of a BPSG film and reduction of micro-scratches on a BPSG film by the CMP method. A BPSG film is deposited over a main surface of a substrate on which MISFETs have been formed, and then, a surface of the BPSG film is planarized by the CMP method. Thereafter, a thermal treatment is performed to the substrate to reflow the BPSG film, thereby removing the micro-scratches on the surface of the BPSG film caused by the polishing. At this time, the amount of polishing of the surface of the BPSG film is controlled within a range of 90 to 300 nm, preferably 100 to 250 nm, and more preferably 120 to 200 nm.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 21, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Shinichi Nakabayashi, Hidekazu Okuda, Kosaku Tachikawa
  • Publication number: 20030124858
    Abstract: For carrying out chemical mechanical polishing while supplying a polishing slurry to a surface of individual wafers running through a mass-production process so as to suppress the occurrence of microscratches by reducing the density of coagulated particles in the polishing slurry used in a chemical mechanical polishing step, the polishing slurry used is allowed to stand in a container for at least 30 days or more, preferably 40 days or more, and more preferably 50 days or more, so that the concentration of coagulated particles having a size of 1 &mgr;m or more is at 200,000 particles/0.5 cc, preferably 50,000 particles/0.5 cc, and more preferably 20,000 particles/0.5 cc.
    Type: Application
    Filed: December 16, 2002
    Publication date: July 3, 2003
    Inventors: Shinichi Nakabayashi, Hisahiko Abe, Katsuhiro Ota
  • Patent number: 6514864
    Abstract: For carrying out chemical mechanical polishing while supplying a polishing slurry to a surface to be processed of individual wafers running through a mass-production process so as to suppress occurrence of microscratches by reducing the density of coagulated particles in the polishing slurry used in a chemical mechanical polishing step, the polishing slurry used is allowed to stand in a condition filled in a container for at least 30 days or over, preferably 40 days or over, and more preferably 50 days or over so that the concentration of coagulated particles having a size of 1 &mgr;m or over is at 200,000 particles/0.5 cc, preferably 50,000 particles/0.5 cc, and more preferably 20,000 particles/0.5 cc.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: February 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Nakabayashi, Hisahiko Abe, Katsuhiro Ota
  • Publication number: 20020160610
    Abstract: A fabrication method of a semiconductor integrated circuit device including polishing the entire area of an edge of a wafer, for example, by using three polishing drums in which a polishing drum polishes the upper surface of the edge of the water relatively, the polishing drum polishes the central portion of the edge of the wafer relatively and a polishing drum polishes the lower surface of the edge of the wafer relatively, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Application
    Filed: March 1, 2002
    Publication date: October 31, 2002
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 6468817
    Abstract: In the manufacturing method, micro scratches are detected without performing a breakdown inspection on wafers flowing through a mass production process. The method comprises: forming an insulating film on main surfaces of a plurality of first wafers which flow through a mass-production process; preparing a dummy wafer for monitoring, on which a silicon-oxide-based insulating film is formed; performing chemical mechanical polishing on the insulating films respectively formed on main surfaces of the plurality of first wafers and the dummy wafer; performing etching on the insulating film of the dummy wafer with use of a solution containing hydrofluoric acid, after the step of performing the chemical mechanical polishing; and measuring a number of scratches on the insulating film of the dummy wafer subjected to the etching.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: October 22, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Nakabayashi, Hisahiko Abe, Hirofumi Tsuchiyama, Yukio Kenbo, Yoshiteru Katsumura
  • Publication number: 20020042154
    Abstract: In the manufacturing method, micro scratches are detected without performing a breakdown inspection on wafers flowing through a mass production process.
    Type: Application
    Filed: August 23, 2001
    Publication date: April 11, 2002
    Inventors: Shinichi Nakabayashi, Hisahiko Abe, Hirofumi Tsuchiyama, Yukio Kenbo, Yoshiteru Katsumura
  • Publication number: 20010044210
    Abstract: For carrying out chemical mechanical polishing while supplying a polishing slurry to a surface to be processed of individual wafers running through a mass-production process so as to suppress occurrence of microscratches by reducing the density of coagulated particles in the polishing slurry used in a chemical mechanical polishing step, the polishing slurry used is allowed to stand in a condition filled in a container for at least 30 days or over, preferably 40 days or over, and more preferably 50 days or over so that the concentration of coagulated particles having a size of 1 &mgr;m or over is at 200,000 particles/0.5 cc, preferably 50,000 particles/0.5 cc, and more preferably 20,000 particles/0.5 cc.
    Type: Application
    Filed: May 15, 2001
    Publication date: November 22, 2001
    Inventors: Shinichi Nakabayashi, Hisahiko Abe, Katsuhiro Ota