Abstract: There is a need to solve a possible system malfunction when a power supply voltage decreases steeply. To solve this problem, a control method is provided for a voltage detection system having an interrupt mode and a reset mode. First and second detection levels are configured. When a power supply voltage is higher than the first detection level, a latch circuit is placed in a first state to enable the interrupt mode. When the power supply voltage becomes lower than or equal to the first detection level, an interrupt signal is generated to change the latch circuit from the first state to a second state and enable the reset mode. A system reset is issued when the power supply voltage becomes lower than or equal to the second detection level in the reset mode.

Abstract: A microcontroller includes a CPU (Central Processing Unit), a data input unit, and an oscillator that supplies a clock signal in response to operational modes of the microcontroller. The operational modes include a STOP mode, a SNOOZE mode and a RUN mode, in the STOP mode, the oscillator and the CPU are stopped, in the RUN mode, the CPU and the data input unit operate using the clock signal supplied from the oscillator, and in the SNOOZE mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives first data, and the microcontroller switches to the RUN mode after the data input unit receives second data using the clock signal.

Abstract: A microcontroller includes a CPU (Central Processing Unit), a data input unit, and an oscillator that supplies a clock signal in response to operational modes of the microcontroller. The operational modes include a STOP mode, a SNOOZE mode and a RUN mode, in the STOP mode, the oscillator and the CPU are stopped, in the RUN mode, the CPU and the data input unit operate using the clock signal supplied from the oscillator, and in the SNOOZE mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives first data, and the microcontroller switches to the RUN mode after the data input unit receives second data using the clock signal.

Abstract: A voltage detection circuit including a voltage selection circuit that outputs a voltage commensurate with a power supply voltage as a first voltage; a detection voltage selection circuit that selects either an external input voltage inputted from an external terminal or the first voltage according to a first control signal, and outputs it as a comparison voltage; a reference voltage generation circuit that generates a reference voltage; a comparator that compares the reference voltage and the comparison voltage, and outputs the comparison result as a detection signal; a control circuit that generates the first control signal so that the detection voltage selection circuit may output either the first voltage or the external input voltage as the comparison voltage by time division, and when a variation of the first voltage is detected, generates the first control signal so that the detection object selection circuit may output the first voltage as the comparison voltage.

Abstract: A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated.

Abstract: A voltage detection circuit including a voltage selection circuit that outputs a voltage commensurate with a power supply voltage as a first voltage; a detection voltage selection circuit that selects either an external input voltage inputted from an external terminal or the first voltage according to a first control signal, and outputs it as a comparison voltage; a reference voltage generation circuit that generates a reference voltage; a comparator that compares the reference voltage and the comparison voltage, and outputs the comparison result as a detection signal; a control circuit that generates the first control signal so that the detection voltage selection circuit may output either the first voltage or the external input voltage as the comparison voltage by time division, and when a variation of the first voltage is detected, generates the first control signal so that the detection object selection circuit may output the first voltage as the comparison voltage.

Abstract: There is a need to solve a possible system malfunction when a power supply voltage decreases steeply. To solve this problem, a control method is provided for a voltage detection system having an interrupt mode and a reset mode. First and second detection levels are configured. When a power supply voltage is higher than the first detection level, a latch circuit is placed in a first state to enable the interrupt mode. When the power supply voltage becomes lower than or equal to the first detection level, an interrupt signal is generated to change the latch circuit from the first state to a second state and enable the reset mode. A system reset is issued when the power supply voltage becomes lower than or equal to the second detection level in the reset mode.

Abstract: A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer between the first and second latch circuits. The area of the first contact pad is larger than that of the second contact pad.

Abstract: A semiconductor circuit is installed on a printed circuit board having a power wiring pattern and a ground wiring pattern that do not intersect. The semiconductor circuit includes a first power supply terminal and a first ground terminal for a first side of the semiconductor circuit, and a second power supply terminal and a second ground terminal for a second side opposing to the first side. The direction from the first power supply terminal to the first ground terminal is the same as the direction from the second power supply terminal to the second ground terminal.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency clock signal as an first clock signal to optimize an operation of the nonvolatile memory, and then to read out circuit block optimization data as another part of the optimization data from the nonvolatile memory in synchronization with a second frequency clock signal as the first clock signal to optimize an operation of the circuit block. The frequency of the first frequency clock signal is lower than that of the second frequency clock signal.

Abstract: A semiconductor circuit is installed on a printed circuit board having a first wiring pattern and a second wiring pattern. The semiconductor circuit includes a first power supply terminal and a first ground terminal which are provided for a first side of the semiconductor circuit. The first power supply terminal is connected with the first wiring pattern. The first ground terminal is connected with the second wiring pattern. A second power supply terminal and a second ground terminal are provided for a second side opposing to the first side. The second power supply terminal is connected with the first wiring pattern and the second ground terminal is connected with the second wiring pattern. The first and second power and ground terminals are arranged such that the first wiring pattern and the second wiring pattern do not intersect in a region of the wiring substrate corresponding to the semiconductor circuit.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A microcomputer includes a circuit block; a nonvolatile memory configured to store optimization data for optimization of an operation of the microcomputer; and an optimization circuit configured to read out memory optimization data as a part of the optimization data from the nonvolatile memory in synchronization with a first frequency clock signal as an first clock signal to optimize an operation of the nonvolatile memory, and then to read out circuit block optimization data as another part of the optimization data from the nonvolatile memory in synchronization with a second frequency clock signal as the first clock signal to optimize an operation of the circuit block. The frequency of the first frequency clock signal is lower than that of the second frequency clock signal.

Abstract: A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer between the first and second latch circuits. The area of the first contact pad is larger than that of the second contact pad.

Abstract: A system clock generating circuit for supplying a system clock to a microproeessor, includes a first oscillator for generating a main clock, and a second oscillator for generating a sub clock which is lower in frequency than the main clock. A twin-clock control circuit receives the main clock and the sub clock and is controlled by the microprocessor. When the microprocessor is in an ordinary operating condition, the twin-clock control circuit generates a (n)-phase system clock which is composed of (n) clocks for each one instruction cycle, where "n" is a positive even number. When the microprocessor is in an electric power saving mode, the twin-clock control circuit also generates a (n/m)-phase system clock which is composed of (n/m) clocks for each one instruction cycle, where "m" is a positive even number but is smaller than "n".