Abstract: A low-noise differential bias circuit is provided which obtains excellent noise characteristics while ensuring excellent distortion characteristics. A collector of a transistor Q11 is connected to a voltage supply point (Vcc) via a resistor R15. A base of the transistor Q11 is connected to a base of a transistor Q1 via resistors R13, R11 connected in series. A connection point between the resistors R11, R13 is connected to the collector of the transistor Q11. A collector of a transistor Q12 is connected to the voltage supply point at connection point A via a resistor R16. A base of the transistor Q12 is connected to a base of a transistor Q2 via resistors R14, R12 connected in series. A connection point between the resistors R12, R14 is connected to the collector of the transistor Q12. By this configuration, a high frequency ground is performed at the connection point A.

Abstract: A prescaler circuit includes: a frequency number switching part including first to sixth D-type flip-flop circuits, first and second AND circuits and first and second OR circuits; and a frequency division switching control part including a third AND circuit, a third OR circuit and first and second NOR circuits. The frequency number switching part has a function of controlling the frequency division among frequency division numbers of 1/N, 1/(N+1) and 1/(N+2) via the first and the second AND circuits by controlling modulus signals input to the first and the second NOR circuits. The frequency division switching control part has a function of controlling the frequency division between ?-frequency-division and 1/16-frequency-division by controlling a modulus signal input to the third AND circuit. A margin for a delay time that causes misoperation at the time of the switching of frequency division numbers can be increased.

Abstract: A prescaler circuit includes: a frequency number switching part including first to sixth D-type flip-flop circuits, first and second AND circuits and first and second OR circuits; and a frequency division switching control part including a third AND circuit, a third OR circuit and first and second NOR circuits. The frequency number switching part has a function of controlling the frequency division among frequency division numbers of 1/N, 1/(N+1) and 1/(N+2) via the first and the second AND circuits by controlling modulus signals input to the first and the second NOR circuits. The frequency division switching control part has a function of controlling the frequency division between ?-frequency-division and 1/16-frequency-division by controlling a modulus signal input to the third AND circuit. A margin for a delay time that causes misoperation at the time of the switching of frequency division numbers can be increased.

Abstract: An object of the present invention is to obtain a frequency division circuit including a flip-flop circuit capable of low-voltage and high-frequency operation. The frequency division circuit has bipolar transistors and MOS transistors. Thus, the circuit includes transistors that are connected to the transistor to which the clock input is input, that execute the differential operation after being input with data input signals, and that output signals of resistors, and also transistors that are similarly connected to the transistor to which Ck is input and that hold signals of resistors, transistors that are connected to the transistor to which Ck is input and that output signals of resistors, and transistors that are connected to the transistor to which NCk is input and that hold signals of resistors.

Abstract: A low-noise differential bias circuit is provided which obtains excellent noise characteristics while ensuring excellent distortion characteristics. A collector of a transistor Q11 is connected to a voltage supply point (Vcc) via a resistor R15. A base of the transistor Q11 is connected to a base of a transistor Q1 via resistors R13, R11 connected in series. A connection point between the resistors R11, R13 is connected to the collector of the transistor Q11. A collector of a transistor Q12 is connected to the voltage supply point at connection point A via a resistor R16. A base of the transistor Q12 is connected to a base of a transistor Q2 via resistors R14, R12 connected in series. A connection point between the resistors R12, R14 is connected to the collector of the transistor Q12. By this configuration, a high frequency ground is performed at the connection point A.