Patents by Inventor Shinichi SEKITA

Shinichi SEKITA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10771085
    Abstract: An analog-to-digital converter includes: a first to an (m+1)-th capacitive element each of which has a first end connected to a first terminal of a comparison circuit and have a predetermined capacitance ratio; and selection circuits which are connected to second ends of the capacitive elements, respectively. Each of the capacitive elements includes: a first electrode disposed in a semiconductor substrate and electrically connected to the second end; a third electrode disposed above the semiconductor substrate to oppose the first electrode and electrically connected to the second end; a second electrode disposed between the first electrode and the third electrode, above the semiconductor substrate, and electrically connected to the first end; a first insulation film disposed between the first and second electrodes; and a second insulation film disposed between the third and second electrodes.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 8, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shinichi Sekita
  • Publication number: 20190165802
    Abstract: An analog-to-digital converter includes: a first to an (m+1)-th capacitive element each of which has a first end connected to a first terminal of a comparison circuit and have a predetermined capacitance ratio; and selection circuits which are connected to second ends of the capacitive elements, respectively. Each of the capacitive elements includes: a first electrode disposed in a semiconductor substrate and electrically connected to the second end; a third electrode disposed above the semiconductor substrate to oppose the first electrode and electrically connected to the second end; a second electrode disposed between the first electrode and the third electrode, above the semiconductor substrate, and electrically connected to the first end; a first insulation film disposed between the first and second electrodes; and a second insulation film disposed between the third and second electrodes.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 30, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shinichi SEKITA
  • Patent number: 10212369
    Abstract: The present solid-state imaging apparatus includes: a light receiving element with a photoelectric conversion function; a readout circuit that reads out pixel information from the light receiving element, and outputs an output voltage; a CDS circuit that is composed of three-stage common source circuits, and generates a pixel signal based on a difference between an output voltage output from the readout circuit at the time of reset and an output voltage output based on the readout of the pixel information, the three-stage common source circuits being connected in series to one another and provided with direct-current cut elements that are each disposed on a corresponding one of input paths of the three-stage common source circuits; and a bias voltage supply circuit that supplies a direct-current bias voltage to gates of transistors of the three-stage common source circuits.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 19, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Shinichi Sekita, Naoki Nomura
  • Publication number: 20180213165
    Abstract: The present solid-state imaging apparatus includes: a light receiving element with a photoelectric conversion function; a readout circuit that reads out pixel information from the light receiving element, and outputs an output voltage; a CDS circuit that is composed of three-stage common source circuits, and generates a pixel signal based on a difference between an output voltage output from the readout circuit at the time of reset and an output voltage output based on the readout of the pixel information, the three-stage common source circuits being connected in series to one another and provided with direct-current cut elements that are each disposed on a corresponding one of input paths of the three-stage common source circuits; and a bias voltage supply circuit that supplies a direct-current bias voltage to gates of transistors of the three-stage common source circuits.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 26, 2018
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shinichi SEKITA, Naoki NOMURA