Abstract: In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.

Abstract: Parallel processors communicate with each other over a network by transmitting messages that include destination processor information. A message controller for each processor in the network receives the messages and checks for faults in the message, particularly in the destination processor number contained in a first word of the message. If a fault occurs in the destination processor number, then the faulty message is transmitted to an appropriate processor for handling the fault. In this way the network operation is not suspended because of the fault and the message is not left in the network as a result of the error occurring in the destination processor number. The processor to which the faulty message is directed is determined by a substitute destination processor number contained in the message or is predetermined and set in another way, such as by a service processor.

Abstract: A parallel processor system including a plurality of processors. When packets of same destination PE number are inputted from different ports, the destination PE number is added with ID numbers of leading ports of split crossbar switches to which the different input ports belong, respectively, by using respective addition circuits, to thereby determine a transfer destination output port for the packets. A plurality of the split crossbar switches having different numbers of input/output ports are realized by partitioning a crossbar switch.

Abstract: A parallel computer network wherein an arbitration circuit for performing arbitrating operation over a plurality of processing requests at the same time at high speed is provided in a crossbar network control circuit to thereby prevent the processing requests not selected from being kept awaited for a long time. The arbitration circuit includes a priority bit change circuit which has a plurality of adders for adding a preset value to the priority information of the each awaited processing request and also has a plurality of comparators for detecting the requests being awaited.

Abstract: Crossbar switches having 2.sup.n +1 ports and computing clusters are arranged so that each crossbar switch is connected to 2.sup.n processors. Auxiliary processors that perform parallel processing administrative functions and input/output functions are arranged at the remainder ports of the crossbar switches. Exchangers are provided to connect each processor and its crossbar switches. Parallel processing may be executed by the 2.sup.n processors independently of processing by the auxiliary processors for speed. One mounting unit is formed of a crossbar switch of one dimension, the processor group connected to that crossbar switch, and all of the crossbar switches of a different dimension that are connected to one of the processors of the one processor group.