Abstract: A dust cover is provided in a cylindrical shape in an axial direction of a suspension apparatus configured to dampen a shock, and is extendable and compressible in the axial direction, or can be bent. A dust cover has a plurality of peak sections provided in the axial direction and configured to protrude outward in a radial direction, a plurality of valley sections provided in the axial direction and configured to protrude inward in the radial direction, and a plurality of connection sections provided in the axial direction and configured to connect the peak sections and the valley sections. At least one of axial concave sections and axial convex sections, which are formed in the axial direction, are provided in at least any of the peak section, the valley section, and the connection section.

Abstract: A cover member is to cover a cylinder and includes a plurality of peaks, a plurality of valleys, and coupling portions, which couple the plurality of peaks to the plurality of valleys. The cover member is expandable and contractable in an alignment direction in which the plurality of peaks and the plurality of valleys are aligned. Each peak of the plurality of peaks includes a depression depressed from an apex of the peak in a direction toward the cylinder, and each valley of the plurality of valleys includes a protrusion protruding from a bottom of the valley in a direction opposite to the cylinder.

Abstract: A cylinder device includes a cylinder that has one end from which a piston rod extends, a pipe-shaped cover member that has an extendable bellows portion and a small-diameter portion whose inner diameter is smaller than an inner diameter of the bellows portion, the cover member being configured to protect the piston rod, and a capping member fitted into the cylinder, the capping member having a convex portion to which the small-diameter portion of the cover member is locked, at an outer periphery, wherein at the small-diameter portion of the cover member, a bulge portion that bulges outside in a radial direction is formed.

Abstract: A cylinder device includes a cylinder that has one end from which a piston rod extends, a pipe-shaped cover member that has an extendable bellows portion and a small-diameter portion whose inner diameter is smaller than an inner diameter of the bellows portion, the cover member being configured to protect the piston rod, and a capping member fitted into the cylinder, the capping member having a convex portion to which the small-diameter portion of the cover member is locked, at an outer periphery, wherein at the small-diameter portion of the cover member, a bulge portion that bulges outside in a radial direction is formed.

Abstract: A dust cover to cover an opening of a housing through which at least one of a shaft and a pipe extends includes a hole-edge portion and a main body. The at least one of the shaft and the pipe is extendable through the through hole. The hole-edge portion defines an edge of a through hole through which the at least one of the shaft and the pipe is extendable. The main body is configured to cover the opening. The main body has a hardness different from a hardness of the hole-edge portion.

Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

Abstract: A cover member is to cover a cylinder and includes a plurality of peaks, a plurality of valleys, and coupling portions, which couple the plurality of peaks to the plurality of valleys. The cover member is expandable and contractable in an alignment direction in which the plurality of peaks and the plurality of valleys are aligned. Each peak of the plurality of peaks includes a depression depressed from an apex of the peak in a direction toward the cylinder, and each valley of the plurality of valleys includes a protrusion protruding from a bottom of the valley in a direction opposite to the cylinder.

Abstract: A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.

Abstract: A dust cover is provided in a cylindrical shape in an axial direction of a suspension apparatus configured to dampen a shock, and is extendable and compressible in the axial direction, or can be bent. A dust cover has a plurality of peak sections provided in the axial direction and configured to protrude outward in a radial direction, a plurality of valley sections provided in the axial direction and configured to protrude inward in the radial direction, and a plurality of connection sections provided in the axial direction and configured to connect the peak sections and the valley sections. At least one of axial concave sections and axial convex sections, which are formed in the axial direction, are provided in at least any of the peak section, the valley section, and the connection section.

Abstract: A cover member having plural peak portions and plural trough portions, and freely stretched and shrunk in an array direction of the plural peak portions and the plural trough portions or freely bent, the cover member includes: a hollow part formed in each of the plural peak portions, the hollow part being hollowed toward an inner side from a peak of each of the plural peak portions, being formed in a circumferential direction, and having edge parts, a bottom part and side parts located between the edge parts and the bottom part. The edge parts of the hollow part are brought into contact with each other before the side parts of the hollow part are brought into contact with each other, when at least one of the plural peak portions is subjected to force in a direction intersecting with the array direction from an outside.

Abstract: A reconfigurable circuit design method includes an input step of inputting design data of a default configuration of a reconfigurable circuit including a plurality of processor elements which perform processing and a first generation step of generating design data obtained by modifying at least one of the processor elements in the reconfigurable circuit with the default configuration.

Abstract: An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a configuration of the reconfigurable circuit.

Abstract: A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories.

Abstract: A cover member having plural peak portions and plural trough portions, and freely stretched and shrunk in an array direction of the plural peak portions and the plural trough portions or freely bent, the cover member includes: a hollow part formed in each of the plural peak portions, the hollow part being hollowed toward an inner side from a peak of each of the plural peak portions, being formed in a circumferential direction, and having edge parts, a bottom part and side parts located between the edge parts and the bottom part. The edge parts of the hollow part are brought into contact with each other before the side parts of the hollow part are brought into contact with each other, when at least one of the plural peak portions is subjected to force in a direction intersecting with the array direction from an outside.

Abstract: A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.

Abstract: A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.

Abstract: A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed.

Abstract: A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register section for setting a content of loop processing on the basis of the context, the loop processing content including an output source of an output signal from each of a set of the reconfigured PEs, an output destination of the output signal, and a condition for outputting the output signal to the output destination; and at least one counter circuit including a loop control section and an output register section that implement the set loop processing, that count the number of implementations of the loop processing implemented by the loop control section, and that output the output signal to the output destination based on the counted number of implementations and the condition.

Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

Abstract: A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.