Patents by Inventor Shinichi SUZAKI

Shinichi SUZAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Operation verification program, operation synchronization method, and error detection apparatus
    Patent number: 11526137
    Abstract: In the conventional semiconductor device, it is impossible for two CPUs to operate memories to be debugged at synchronous timings. According to one embodiment, the operation verifying program analyzes the operation verifying command received by the first semiconductor device 10 from the external device 31 by its own device (S32), transfers the operation verifying command to the second semiconductor device 20 (S31, S41), also analyzes the operation verifying command in the second semiconductor device 20 (S42), outputs the trigger signal (S34, S44) to the first semiconductor device 10 from the second semiconductor device 20 based on the result of the analysis, writes the memory setting values included in the operation verifying command to the memories in the respective semiconductor device (S35, S45) based on the trigger signal, and restarts the device operation based on the written memory setting values.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 13, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Suzaki, Toshihiro Kawano
  • OPERATION VERIFICATION PROGRAM, OPERATION SYNCHRONIZATION METHOD, AND ERROR DETECTION APPARATUS
    Publication number: 20200218206
    Abstract: In the conventional semiconductor device, it is impossible for two CPUs to operate memories to be debugged at synchronous timings. According to one embodiment, the operation verifying program analyzes the operation verifying command received by the first semiconductor device 10 from the external device 31 by its own device (S32), transfers the operation verifying command to the second semiconductor device 20 (S31, S41), also analyzes the operation verifying command in the second semiconductor device 20 (S42), outputs the trigger signal (S34, S44) to the first semiconductor device 10 from the second semiconductor device 20 based on the result of the analysis, writes the memory setting values included in the operation verifying command to the memories in the respective semiconductor device (S35, S45) based on the trigger signal, and restarts the device operation based on the written memory setting values.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 9, 2020
    Inventors: Shinichi SUZAKI, Toshihiro KAWANO