Abstract: In a semiconductor device according to an aspect of the invention, a direction in which a fourth metal interconnection layer located on a semiconductor layer is extended is orthogonal to a direction in which third interconnection layers ML30 and ML37 located on the fourth interconnection layer are extended. Thus, even in a case where a stress is applied from outside to bonding pads BP1 and BP2 located above, the stress is wholly dispersed by the third interconnection layers and the fourth interconnection layer which are laminated to intersect with each other, and stress concentration on a particular point can be relieved to restrain deterioration in semiconductor device strength to a minimum. Accordingly, it is possible to provide the semiconductor device having a structure in which productivity of the semiconductor device can be improved while the stress concentration applied from outside on the particular point of the bonding pad is relieved.

Abstract: In a semiconductor device according to an aspect of the invention, a direction in which a fourth metal interconnection layer located on a semiconductor layer is extended is orthogonal to a direction in which third interconnection layers ML30 and ML37 located on the fourth interconnection layer are extended. Thus, even in a case where a stress is applied from outside to bonding pads BP1 and BP2 located above, the stress is wholly dispersed by the third interconnection layers and the fourth interconnection layer which are laminated to intersect with each other, and stress concentration on a particular point can be relieved to restrain deterioration in semiconductor device strength to a minimum. Accordingly, it is possible to provide the semiconductor device having a structure in which productivity of the semiconductor device can be improved while the stress concentration applied from outside on the particular point of the bonding pad is relieved.

Abstract: A fabricating method of a semiconductor device includes preparing a compound semiconductor substrate including an active layer epitaxially grown on the substrate, forming a test element group FET (TEGFET) having a characteristic value on the compound semiconductor substrate and measuring a characteristic value of the TEGFET, forming an FET having a characteristic value on the compound semiconductor substrate, measuring the characteristic value of the FET, obtaining a variation of the carrier concentration of the active layer of the FET relative to a required value by comparing the measured characteristic value of the FET with reference data obtained from the TEGFET and correcting the variation by implanting ions under conditions that correct the variation. Therefore, after forming a gate electrode of the FET, the carrier concentration of the active layer of the FET is corrected, so the the yield of the device is improved.

Abstract: A method of performing element separation by ion implantation for a compound semiconductor device includes performing first ion implantation into the entire contour of the device periphery region to produce a first insulating region having a region of the maximum ion implantation concentration serving as an insulation destruction relaxing layer within a buffer layer located at the deepest position of epitaxial growth layers. Even when there is a distribution of implanted ions in the depth direction at the thermal processing in the wafer process, the implanted ions diffuse so that the concentration of ions is uniform in the depth direction and a thermally stable ion implantation concentration as well as stable device characteristics are obtained.

Abstract: A method of element isolation includes implanting ions in a compound semiconductor substrate at the periphery of a semiconductor device in the substrate to produce a first insulating region having a region of maximum implanted ion concentration within a buffer layer at the deepest of multiple epitaxially grown layers. Even when there is a redistribution of implanted ions due to thermal processing, the implanted ions diffuse so that the concentration of ions becomes uniform in the depth direction and a thermally stable ion implantation concentration distribution as well as stable device characteristics are obtained. A second insulating region having a resistivity different from that of the first insulating region may be produced in a second ion implantation step, relaxing an electric field at the interface between the insulating region and a gate electrode, securing a stable, high gate junction breakdown voltage. Thus, a highly reliable element isolating technique and a highly reliable device are obtained.

Abstract: An electrically isolated MESFET includes a compound semiconductor substrate; a plurality of compound semiconductor layers disposed on the compound semiconductor substrate; a MESFET structure in a prescribed region of the compound semiconductor layers; an electrically isolating region in the compound semiconductor layers surrounding and electrically isolating the MESFET structure from the compound semiconductor layers outside the electrically isolating region, wherein the compound semiconductor layer most remote from the compound semiconductor substrate has the highest conductivity of the compound semiconductor layers; a recess penetrating the compound semiconductor layer most remote from the compound semiconductor substrate and at least the compound semiconductor layer adjacent the compound semiconductor layer most remote from the compound semiconductor substrate, the recess dividing the compound semiconductor layer most remote from the compound semiconductor substrate into mutually separated first and second

Abstract: A photoelectric transducer is composed of a photosensitive element 12 and an auxiliary light source 14. In a preferred embodiment, the photosensitive element 12 has an upper transparent electrode 6, a lower transparent electrode 7, a amorphous silicon germanium semiconductor 8, and an transparent glass substrate 11. Incident light 15 irradiates an upper light-receiving surface 9 of the amorphous silicon germanium semiconductor 8 through the upper transparent electrode 6, and the photoelectric current generated by photoelectric conversion at the amorphous silicon germanium semiconductor 8 flows through by the upper transparent electrode 6 and the lower transparent electrode 7. In one embodiment of the invention, the auxiliary light source 14 is a blue light source provided by the right side of the upper transparent electrode 6 to irradiate the photosensitive element 12, which enables selective amplification of the sensitivity of the photoelectric transducer to the incident light in the near infrared region.