Abstract: A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode.

Abstract: A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode.

Abstract: A memory having a storage capacity of storing pixel data of one frame is employed as a bank for display of bidirectional predictive encoded pixel data, and time difference between a timing for starting decoding of a given frame in a decoding unit and that for starting display of pixel data of the given frame in a display unit is set at one field time. The storage capacity of a memory device employed for display of pixel data is reduced in a picture decoding and display unit having a decoding and display function.

Abstract: An A/V signal pickup unit receives an audio digital data stream. A CPU carries out a decode process, and adds tag data indicating the attribute of audio sample data to provide the same to an audio signal converter unit. The audio signal converter unit controls the timing of the output operation of sample data according to the tag data.

Abstract: Each of element processors arranged in correspondence to pixels of a template block and a search window block respectively includes an A register and a B register provided in parallel with each other for storing search window block pixel data respectively, and a T register for storing template block pixel data. Motion vector evaluation value calculation is performed through a first one of the A and B registers and the pixel data stored in the T register, while operated data is transferred to the second one of the A and B registers from the first one of the A and B registers in parallel with the calculation operation, for storing head search window block pixel data of a next search window. A motion vector is detected at a high speed in excellent coding efficiency.

Abstract: A synchronous semiconductor memory device is utilized as an image data storage memory, and at most two pixels as one word are alternately stored in first and second banks of the synchronous semiconductor memory device. Respective pixel data of two types of color-difference signals as to the same pixel are stored in the same address position of the banks of the synchronous semiconductor memory device. Necessary data can be transferred by the burst length of the synchronous semiconductor memory device while suppressing overhead of page change to the minimum by alternately accessing the first and second banks.

Abstract: When a macro block synchronizing signal indicating starting of processing is asserted in processing of one processing section which is formed by a macro block header and a macro block, block data of the macro block are decoded in synchronization with the assertion of MBSYNC, and next macro block header information is analyzed in continuation in the processing section. The assertion of the next MB synchronizing signal is stopped until prescribed conditions are established. Processing of the block data of the macro blocks is regularly executed from starting of one processing section, whereby utilization efficiency of operational processors is improved.

Abstract: A data comparator detects the coincidence or non-coincidence of the logical states between two adjacent bits of the plural bit input data and applies the comparison result signal to a non-coincident bit detection circuit. A mask generator decodes a shift select signal indicating the amount of shift to produce mask data and applies the produced mask data to a non-coincident bit detection circuit. The non-coincident bit detection circuit masks the output of the data comparator on the basis of the mask data and decides whether or not an overflow is produced from the masked output of the data comparator to output the result of decision.

Abstract: A general object of the present invention is to provide a latch of which demand is small. In a half-latch 101, control signals T2 and T2C which vary at late timings are applied to a main unit for data input (update) operation while control signals T1 and T1C which vary at early timings are applied to a feedback unit for data retaining operation. The data input (update) operation is never started until the data retaining operation is completed. The data retaining operation is practiced by retaining two signals having a negative logic relation with each other in a loop made up with two inverters. A signal related to retension of data and a signal newly input never reside in the same signal line. Thus, collision of those signals is avoided, and consequently, through-current due to the collision of the signals can be reduced.

Abstract: A motion vector detector includes a processor array having a plurality of processing elements arranged in a two dimensional array. Each of the processing elements includes storage elements for storing search window data of a reference frame and associated template block date of a current frame and a circuit for obtaining an absolute difference of the stored search window data and template data. Each processing element shifts the stored data to an adjacent processing element in a one-way direction on a data transfer path. The processing elements shift the stored search window data while holding the template block data. A displacement vector is calculated in each cycle of the shifting of the search window data by a summation unit receiving outputs of the processing elements in parallel. A comparison unit receives outputs of the summation unit to detect a motion-vector for the template block.

Abstract: A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.

Abstract: A semiconductor integrated circuit device includes a memory cell array for storing data to be processed, and an operational unit for effecting a predetermined operation on the data read from the memory cell array. The memory cell array has first and second regions for storing first and second data words of first and second groups. The first data words and second data words each include a plurality of data bits. The first region includes a plurality of bit arrays for storing data bits of the same digit in the first data words, and the second region includes a plurality of bit arrays for storing data bite of the same digit in the second data words. The bit arrays of the first and second groups are arranged alternately in the order of digits of the data words. The bit arrays storing the data bits of the same digit form one subarray. The data bits in one data word are stored in the same positions of the bit arrays. The operational unit includes operational circuits each corresponding to one of the subarrays.

Abstract: An improved M-bit accumulator for increasing speed and reducing circuit size includes an N-bit (N<M) adder, a first latch having an input coupled to the output of the adder and an output coupled to an input of the adder for latching the adder output when a first clock signal is asserted, an (M-N) bit incrementer, a second latch having an input coupled to the output of the incrementer and an output coupled to the input of the incrementer for latching the incrementer output when a second clock signal is asserted, and a clock generating circuit for asserting the second clock signal in synchronism with the first clock signal only when a carry signal is generated by the adder.

Abstract: Each of memory cells of a semiconductor memory device comprises a transistor connected between a node and a node, a transistor connected between the node and a node, a transistor connected between a node and a node, and a transistor connected between node and a node. Each of the nodes is connected to either of a first potential line and a second supply line in a program unit when it is manufactured, and each of the nodes is connected to either of the first and the second ground lines in a program unit when it is manufactured.A supply potential is supplied to the first supply line, and the supply potential or the ground potential is selectively supplied to the second supply line. The ground potential is supplied to the first ground line, and the ground potential or the supply potential is selectively supplied to the second ground line.

Abstract: A data bus has a bit length of 2 words, and is divided into two bit groups, each of which corresponds to one word. Therefore, the data bus can simultaneously transfer data of two words. A register, a data operation part of a CPU, a RAM and a ROM is connected to the data bus. Even if there is generated data of two words to be transferred in these registers, the data operation part, the RAM and the ROM, the data bus can simultaneously transfer the data. In order to prevent conflict of data on the data bus, there are provided a bus driver, a multiplexer and a bus selector.

Abstract: A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.

Abstract: An SRAM adapted for changing the sequence of data. A counter 7 generates a sequentially increasing address signal. A write designation circuit 2a sequentially designates a memory cell row to be selected for writing in response to the address signal. Conversely, a read designation circuit 3a designates a memory cell row in response to the address signal in a sequence determined by a predetermined rule. The generation of an address signal, which changes in a complicated manner and is required for changing the sequence of data, is not required, so that the amount of the operation process by the CPU is decreased.

Abstract: A one-dimensional discrete cosine transform processor of N (N: positive integer)-term input data X includes a preprocessing section for carrying out addition and subtraction of (i)th-term data x (i) and (N-i)th-term data x (N-1) of input data X, and a unit for performing a product sum operation for sets of intermediate data subjected to preprocessing by addition and sets of intermediate data subjected to preprocessing by subtraction, respectively. The product sum operation unit includes a data rearranging unit for outputting, in parallel and in order, bit data of the same figure of a set of data, a partial sum generator for generating a partial sum by using the parallel bit data as an address, and an accumulator for accumulating outputs of the partial sum generator.

Abstract: The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal. The select gate includes a first gate for receiving and transferring a first logic signal to an output node, and a second gate for receiving and transferring a second logic signal to the output node. The first and second gates turn on complementarily to each other. The first gate has an output load capacitance viewed from the output node less than that of the second gate. The first gate receives, as the first logic signal, a signal not required to be transmitted at a high speed, or a signal of a predetermined logic level or a fixed level. The second gate receives, as the second signal, a signal to be transmitted at a high speed. Since the second gate has a less output load capacitance, the second gate is allowed to transmit a signal at a high speed.

Abstract: A microprocessor with an improved register part is disclosed. The register part includes a plurality of registers for holding data and adding circuits connected to the outputs of predetermined two registers. Adding circuits are provided as a preceding operation circuit and a part of the operation to be executed in an ALU or a multiplier is carried out in the preceding operation circuit. At the time two data to be used in an operation are applied to the predetermined two registers, addition is started in the preceding operation circuit. Therefore, the number of instructions required for carrying out the operation is reduced thereby realizing faster processing.