Patents by Inventor Shinichi Watarai

Shinichi Watarai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8110878
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: February 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Publication number: 20110266631
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Application
    Filed: July 8, 2011
    Publication date: November 3, 2011
    Inventors: Naozumi MORINO, Atsushi HIRAIWA, Kazutoshi OKU, Toshiaki ITO, Motoshige IGARASHI, Takayuki SASAKI, Masao SUGIYAMA, Hiroshi YANAGITA, Shinichi WATARAI
  • Patent number: 7982271
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Publication number: 20110024847
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Application
    Filed: October 11, 2010
    Publication date: February 3, 2011
    Inventors: NAOZUMI MORINO, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Patent number: 7821076
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Grant
    Filed: April 12, 2009
    Date of Patent: October 26, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
  • Publication number: 20090278204
    Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
    Type: Application
    Filed: April 12, 2009
    Publication date: November 12, 2009
    Inventors: Naozumi MORINO, Atsushi HIRAIWA, Kazutoshi OKU, Toshiaki ITO, Motoshige IGARASHI, Takayuki SASAKI, Masao SUGIYAMA, Hiroshi YANAGITA, Shinichi WATARAI
  • Publication number: 20090179247
    Abstract: A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 16, 2009
    Inventors: Masako FUJII, Shigeki Obayashi, Naozumi Morino, Atsushi Hiraiwa, Shinichi Watarai, Takeshi Yoshida, Kazutoshi Oku, Masao Sugiyama, Yoshinori Kondo, Yuichi Egawa, Yoshiyuki Kaneko
  • Patent number: 5095319
    Abstract: An optical beam apparatus includes a light emission device, a driver for driving the light emission device with the applied VIDEO signal, an integral circuit for estimating a drop of the quantity of light emited by the light emission device from the VIDEO signal applied, and a light output control circuit for controlling the driver in compliance with the estimated result so that the quantity of light emitted by the light emission device becomes constant.
    Type: Grant
    Filed: August 23, 1989
    Date of Patent: March 10, 1992
    Assignee: Fujitsu Limited
    Inventors: Shinichi Watarai, Shunji Kitagawa, Yoji Houki
  • Patent number: 5066978
    Abstract: The image forming device of this invention is related to a device such as a duplicator, a printer, a facsimile or the like in which a printing operation is carried out by utilizing an electrophotographic recording system and an electrostatic recording system, wherein the device includes a plurality of consumable working parts including at least a developing unit, a drum unit, a fixing unit, and a transfer unit, and the device further includes a unit for integrating the working time of each of the working parts, a memory for storing the integrated working time of each working part, a lifetime setting unit in which a predetermined lifetime of each working part is set, and a generator for generating an exchange requirement signal for at least one of the working parts when the integrated working time of the working part reaches the lifetime of the part set in the lifetime setting unit, whereby an image forming device having a system in which these consumable working parts can be exchanged at correct intervals, re
    Type: Grant
    Filed: May 31, 1989
    Date of Patent: November 19, 1991
    Assignee: Fujitsu Limited
    Inventors: Shinichi Watarai, Megumi Yasuda, Yoji Houki, Yukio Nishio
  • Patent number: 4996567
    Abstract: A method of controlling a fuser unit of an image-forming apparatus such as a laser printer, in a warming-up stage, so that excess mechanical and electrostatic stresses are not imposed on the process elements.
    Type: Grant
    Filed: May 9, 1989
    Date of Patent: February 26, 1991
    Assignee: Fujitsu Limited
    Inventors: Shinichi Watarai, Megumi Yasuda, Yoji Hoki, Makoto Inoue
  • Patent number: 4986528
    Abstract: A skew of a print medium sheet generally occurs when the sheet is fed to an image-forming area in an image-forming apparatus, for example, an electronics image-forming printer, from a pile of such sheets. An apparatus according to the present invention is provided with a plurality of pairs of feed rollers between the pile and the image-forming area, and a skew of a sheet is corrected every time the sheet comes in contact with each pair of rollers which are not rotating for a predetermined time, so that even a large skew can be corrected by the time the sheet reaches the image-forming area.
    Type: Grant
    Filed: June 2, 1989
    Date of Patent: January 22, 1991
    Assignee: Fujitsu Limited
    Inventors: Shinichi Watarai, Yoji Houki, Tomohiro Nonomura
  • Patent number: 4966356
    Abstract: A sheet feed apparatus of a recording apparatus, for feeding a sheet one-by-one from a stack of cut sheets, includes cassettes which are stacked one above the other. Each cassette has a common sheet sub-passage passing through the cassette from bottom to top. The sub-passages are aligned to form a common sheet feed passage which passes through the stack of the cassettes from bottom to top when all the cassettes are set in a normal position within the recording apparatus. Sheet feed passages formed in the cassettes are disposed end-to-end.
    Type: Grant
    Filed: September 27, 1988
    Date of Patent: October 30, 1990
    Assignee: Fujitsu Limited
    Inventors: Keiji Ohyabu, Shinichi Watarai, Hideaki Sano
  • Patent number: 4965640
    Abstract: An image forming apparatus has upper and lower frames. A fixing unit detachably mounted on one frame is provided with a heated roller and a pressure roller. One end of a lever is positioned to be pushed by the other frame when the frames are in a closed condition, and the other end of the lever pushes the pressure roller at both ends of its shaft transversally towards the heated roller so as to pinch therebetween and heat a sheet having a toner image thereon. When the frames are disengaged and moved to their opened condition the pressure on the lever is released, whereupon the pressure roller separates from the heated roller so that the pressure on the sheet is released to facilitate easy removal of the sheet.
    Type: Grant
    Filed: March 9, 1989
    Date of Patent: October 23, 1990
    Assignee: Fujitsu Limited
    Inventors: Shinichi Watarai, Makoto Inoue, Keiji Ohyabu
  • Patent number: 4896191
    Abstract: A gap produced between a sheet intruding guide and a surface of a drum is kept to a predetermined value with an allowable tolerance by positioning the sheet intruding guide together with an image transcription unit placed under the drum and constantly pushed toward the drum surface so that a space between the drum surface and the image transcription unit is kept constant. The sheet intruding guide can be lifted up and held away from the image transcription unit when the drum is removed upward, and released from the holding and set back to its regular position mechanically when the drum is lowered back to its regular position.
    Type: Grant
    Filed: September 7, 1988
    Date of Patent: January 23, 1990
    Assignee: Fujitsu Limited
    Inventors: Keiji Ohyabu, Youji Houki, Shinichi Watarai, Tomohiro Nonomura
  • Patent number: 4878428
    Abstract: In a high speed printing station, cut sheets are separated one by one sequentially and transferred through the printing station. When a sheet jamming occurs in the feeding unit all sheet transport means are stopped, the previous sheets remaining and moving in the printing and ejecting units are wasted and components in the printing unit are contaminated by toner powder. The control method of the present invention comprises steps of (a) detecting the sheet jamming occurring in the feeding unit by a first sensor, (b) stopping the transporting means in the feeding unit only, (c) continuing operation of other transport means until the second sensor in the ejecting unit detects an ejection of all previous sheets in the printing and ejecting units, and (d) stopping the other transport means. The sheets except the jammed one become available for use and the contamination by toner powder is avoided.
    Type: Grant
    Filed: August 10, 1988
    Date of Patent: November 7, 1989
    Assignee: Fujitsu Limited
    Inventor: Shinichi Watarai