Abstract: A method for producing a magnetostrictive material and a method for increasing the value of magnetostriction can increase the value of magnetostriction of magnetostrictive materials used, for example, in vibration power generation and force sensors utilizing inverse magnetostriction phenomenon. A magnetostrictive material having a value of magnetostriction of 100 ppm or more is produced by melting and casting an alloy material in the composition of range of 67-87 wt % Co with the balance consisting of Fe and unavoidable impurities and then performing hot forging. Furthermore, a magnetostrictive material having a value of magnetostriction of 130 ppm or more can be produced by performing cold rolling after the hot forging. Heat treatment at 400-1000° C. may also be performed after hot working or cold working.

Abstract: A method of labeling of image data includes reading the image data sequentially with units of two successive pixels and providing one label to a target unit of two successive pixels in the image data when a preliminary label is to be assigned to at least one of the two successive pixels of the target unit. And an image processing apparatus includes a memory configured to store image data, a processor configured to process the image data with units of two successive pixels and to provide one label to a target unit of two successive pixels when a preliminary label is to be assigned to at least one of the two successive pixels of the target unit and a memory controller arranged between the memory and the processor and configured to control reading and writing the image data.

Abstract: An image processing circuit comprising a plurality of line buffers is provided. Each line buffer stores pixel data of a plurality of pixels as line data, the plurality of pixels configuring a single image line of an image. A first image processing part performs a first image processing task on original image data provided from the exterior by using the line data stored in at least one of the line buffers, and provides processed image data. A second image processing part performs a second image processing task on the processed image data provided from the first image processing part by using the line data stored in at least one of the line buffers, and provides processed image data. A line buffer selector selectively connects the first image processing part and the second image processing part to any number of line buffers. An output path selector selects one of an output path that skips the second image processing task and an output path that performs the second image processing task.

Abstract: An image processing apparatus includes a plurality of processor elements including registers and configured to process respective data items, a global processor configured to control the plurality oaf processor elements; the global processor and the plurality of processor elements constituting an SIMD microprocessor, and a data control device coupled to a data transfer port for accessing the registers, the processor elements configured to perform a contiguity check and tentative labeling of pixels adjacent in a sub-scan direction as parallel processes with respect to binary image data, the data control device configured to perform a contiguity check and tentative labeling of pixels adjacent in a main scan direction as consecutive processes, and the parallel processes performed ahead of the consecutive processes with respect to a line of interest in the binary image data.

Abstract: An image processing apparatus includes a plurality of processor elements including registers and configured to process respective data items, a global processor configured to control the plurality oaf processor elements; the global processor and the plurality of processor elements constituting an SIMD microprocessor, and a data control device coupled to a data transfer port for accessing the registers, the processor elements configured to perform a contiguity check and tentative labeling of pixels adjacent in a sub-scan direction as parallel processes with respect to binary image data, the data control device configured to perform a contiguity check and tentative labeling of pixels adjacent in a main scan direction as consecutive processes, and the parallel processes performed ahead of the consecutive processes with respect to a line of interest in the binary image data.

Abstract: An image processing apparatus includes a plurality of processor elements including registers and configured to process respective data items, a global processor configured to control the plurality of processor elements; the global processor and the plurality of processor elements constituting an SIMD microprocessor, and a data control device coupled to a data transfer port for accessing the registers, the processor elements configured to perform a contiguity check and tentative labeling of pixels adjacent in a sub-scan direction as parallel processes with respect to binary image data, the data control device configured to perform a contiguity check and tentative labeling of pixels adjacent in a main scan direction as consecutive processes, and the parallel processes performed ahead of the consecutive processes with respect to a line of interest in the binary image data.

Abstract: An image processing circuit comprising a plurality of line buffers is provided. Each line buffer stores pixel data of a plurality of pixels as line data, the plurality of pixels configuring a single image line of an image. A first image processing part performs a first image processing task on original image data provided from the exterior by using the line data stored in at least one of the line buffers, and provides processed image data. A second image processing part performs a second image processing task on the processed image data provided from the first image processing part by using the line data stored in at least one of the line buffers, and provides processed image data. A line buffer selector selectively connects the first image processing part and the second image processing part to any number of line buffers. An output path selector selects one of an output path that skips the second image processing task and an output path that performs the second image processing task.

Abstract: A parallel processor includes a global processor which interprets a program and control controls the entirety of the parallel processor. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data. The global processor outputs a control signal to the plurality of processor elements, and, thereby, sets processor-element numbers corresponding to the plurality of processor elements as input values of the operation arrays, respectively.

Abstract: A parallel processor includes a global processor which interprets a program and controls the entirety of the parallel processor. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data. The global processor outputs a control signal to the plurality of processor elements, and, thereby, sets processor-element numbers corresponding to the plurality of processor elements as input values of the operation arrays, respectively.

Abstract: An image processing circuit comprising plural line buffers is provided. Each line buffer stores pixel data of plural pixels as line data. A first image processing part performs a first image processing task on original image data provided from the exterior by using the line data stored in at least one of the line buffers. A second image processing part performs a second image processing task on the processed image data from the first image processing part by using the line data stored in at least one of the line buffers. A line buffer selector selectively connects the first image processing part and the second image processing part to any number of line buffers. An output path selector selects one of an output path that skips the second image processing task and an output path that performs the second image processing task.

Abstract: A method of labeling of image data includes reading the image data sequentially with units of two successive pixels and providing one label to a target unit of two successive pixels in the image data when a preliminary label is to be assigned to at least one of the two successive pixels of the target unit. And an image processing apparatus includes a memory configured to store image data, a processor configured to process the image data with units of two successive pixels and to provide one label to a target unit of two successive pixels when a preliminary label is to be assigned to at least one of the two successive pixels of the target unit and a memory controller arranged between the memory and the processor and configured to control reading and writing the image data.

Abstract: A hydrogen permeation membrane having excellent hydrogen permeability and hydrogen embrittlement resistance, and a production method thereof. This membrane is made of a niobium alloy foil having an amorphous crystal structure, the niobium alloy foil comprising 5 to 65 atomic % of at least one member selected from the group consisting of Ni, Co and Mo as a first additive element and 0.1 to 60 atomic % of at least one member selected from the group consisting of V, Ti, Zr, Ta and Hf as a second additive element together with the balance of Nb as an indispensable constituent element wherein 0.01 to 20 atomic % of Al and/or Cu may be contained as a third additive element. This alloy foil can be produced through a method comprising preparing a metal mixture of the above formulation, heating the metal mixture to the melting point or higher in an inert gas so as to melt the same and forming the melt into a film (foil) according to a liquid quenching technique.

Abstract: An image processing apparatus includes a plurality of processor elements including registers and configured to process respective data items, a global processor configured to control the plurality of processor elements; the global processor and the plurality of processor elements constituting an SIMD microprocessor, and a data control device coupled to a data transfer port for accessing the registers, the processor elements configured to perform a contiguity check and tentative labeling of pixels adjacent in a sub-scan direction as parallel processes with respect to binary image data, the data control device configured to perform a contiguity check and tentative labeling of pixels adjacent in a main scan direction as consecutive processes, and the parallel processes performed ahead of the consecutive processes with respect to a line of interest in the binary image data.

Abstract: The present invention is related to branch instructions in a pipeline process of a microprocessor system. The microprocessor system executes branch prediction if a conditional branch instruction code calls for branch prediction, and on the other hand, suspends successive instruction execution until a branch evaluation of the conditional branch instruction settles if the conditional branch instruction code does not call for branch prediction.

Abstract: An image processing circuit comprising a plurality of line buffers is provided. Each line buffer stores pixel data of a plurality of pixels as line data, the plurality of pixels configuring a single image line of an image. A first image processing part performs a first image processing task on original image data provided from the exterior by using the line data stored in at least one of the line buffers, and provides processed image data. A second image processing part performs a second image processing task on the processed image data provided from the first image processing part by using the line data stored in at least one of the line buffers, and provides processed image data. A line buffer selector selectively connects the first image processing part and the second image processing part to any number of line buffers. An output path selector selects one of an output path that skips the second image processing task and an output path that performs the second image processing task.

Abstract: The present invention is related to branch instructions in a pipeline process of a microprocessor system. The microprocessor system executes branch prediction if a conditional branch instruction code calls for branch prediction, and on the other hand, suspends successive instruction execution until a branch evaluation of the conditional branch instruction settles if the conditional branch instruction code does not call for branch prediction.

Abstract: When data that does not fill a bit size (32 bits) of a first register is stored in the first register, 8-bit data is supplied from a second register or a first constant generator to unfilled higher 16 bit positions of the first register, and a second constant generator supplies 8-bit data to fill the remaining bit positions in the first register.

Abstract: A global processor interprets a program and control entirety. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data, wherein the global processor outputs a control signal to the plurality of processor elements, and, thereby, sets processor-element numbers corresponding to the plurality of processor elements as input values of the operation arrays, respectively.

Abstract: A microprocessor apparatus executes a program including an instruction which indicates an address for taking out an operand from a main memory in a predetermined addressing mode which belongs to a displacement-adding register indirect addressing mode. The microprocessor includes address generating portion for shifting by a predetermined number of bits the value of a displacement which is indicated by the instruction, adding the thus-shifted value to the value stored in a predetermined register and thus generating an effective address, when the operand of the instruction is taken out from the main memory.

Abstract: When an interrupt request signal is input, a microprocessor checks, upon termination of an instruction cycle being executed, whether the interrupt request is masked. If the interrupt request is not masked, the microprocessor saves the content of the program counter and the processor status register to a stack. If an extended interrupt request signal is at a high level, the microprocessor sets the bus status signals to a unique state so that a data bus is in a high impedance state. An interrupt controller outputs mask flag data to the data bus so that the mask flag data is saved to a stack. Thereafter, the three-byte data is fetched from a vector address and stored in the program counter. When the mask flag data is to be restored, the mask flag data is read while the bus status signals are set to the unique state.