Abstract: A battery-cell structure of a battery is constructed to have a resinous spacer 5 with a frame shape surrounding thick central portions between a battery cell 3 arranged at an upper side and a battery cell 4 arranged at a lower side, and ventilation portions 62 and 64 that are provided in the resinous lower case 6 to communicate the exterior with depressed portions 61 of the resinous lower case 6 and have an up- and down symmetrical shape and size. It is constructed so that the battery cell 3 arranged at the upper side and the battery cell 4 arranged at the lower side are put in a vertical direction between the resinous lower case 6, the spacer 5 and the upper case 2.

Abstract: An ultrasonic welder includes an anvil, a horn configured to sandwich a first member placed on the anvil and a second member placed on the first member with the anvil, and transmit ultrasonic vibration to the second member, so as to join the first and second members, a vibration detector configured to detect a condition of the vibration transmitted to the first member from the second member, and a controller configured to stop the ultrasonic vibration of the horn according to the detected condition of the vibration.

Abstract: A semiconductor integrated circuit device has first and second receivers and first and second transmitters. The first receiver has a first clock data recovery (CDR) circuit, and the second receiver has a second CDR circuit. Each of these first and second CDR circuits receives serial data, recovers a clock from the received serial data, and changes the phase of the generated clock. The first transmitter has a first serializer (SER), and the second transmitter has a second SER. The first SER converts parallel data into serial data synchronized with a transmit clock or the clock generated by the first CDR circuit. The second SER converts parallel data into serial data synchronized with a transmit clock or the clock generated by the second CDR circuit.

Abstract: An object is to provide a navigation apparatus capable of outputting geographic information without depending on a display. When determining at step ST11 that a destination is assigned, the navigation apparatus interprets geography of an area around the assigned destination at step ST12, and generates geographic information for indicating the geography of the area around the destination as a voice output. Thereafter, the navigation apparatus outputs the voice output indicating the inputted geographic information through a loudspeaker.

Abstract: A structure is disclosed for fixing an electronic device having a heat-releasing plate to a substrate. The structure includes a substrate, a land portion which is formed on a front face of the substrate and on which said heat-releasing plate of the electronic device is to be soldered, a through-hole formed in and penetrating said substrate and said land portion. The through-hole is adapted to release heat generated in the electronic device. The structure further includes a partitioning portion provided to be positioned between the heat-releasing plate and the land portion. The partitioning portion is adapted for preventing a solder, which should partially run out from a specific edge portion of the heat-releasing plate on soldering the heat-releasing plate to the land portion, from partially flowing into the through-hole.

Abstract: The present invention provides a gas turbine capable of reducing energy consumption while suppressing a so-called cat back phenomenon. The gas turbine includes a combustor-accommodating chamber casing for accommodating therein a combustor which burns fuel and air compressed by a compressor to generate combustion gas and which injects the combustion gas to a turbine. The gas turbine also includes a first air supply passage and a second air supply passage on an upper portion of the combustor-accommodating chamber casing in the vertical direction. The first air supply passage discharges air toward the compressor in the combustor-accommodating chamber casing. The second air supply passage discharges air in a direction different from that of the first air supply passage.

Abstract: An object is to provide a navigation apparatus capable of outputting geographic information without depending on a display. When determining at step ST11 that a destination is assigned, the navigation apparatus interprets geography of an area around the assigned destination at step ST12, and generates geographic information for indicating the geography of the area around the destination as a voice output. Thereafter, the navigation apparatus outputs the voice output indicating the inputted geographic information through a loudspeaker.

Abstract: A structure is disclosed for fixing an electronic device having a heat-releasing plate to a substrate. The structure includes a substrate, a land portion which is formed on a front face of the substrate and on which said heat-releasing plate of the electronic device is to be soldered, a through-hole formed in and penetrating said substrate and said land portion. The through-hole is adapted to release heat generated in the electronic device. The structure further includes a partitioning portion provided to be positioned between the heat-releasing plate and the land portion. The partitioning portion is adapted for preventing a solder, which should partially run out from a specific edge portion of the heat-releasing plate on soldering the heat-releasing plate to the land portion, from partially flowing into the through-hole.

Abstract: A DMA controller including a request queue for holding DMA transfer requests clears only the request queue without executing unnecessary DMA transfers and provides information about the states of the queue. A DMA controller is configured to enable data transfer control with respect to plural channels and includes a request queue capable of holding the identification information of channels concerned in plural data transfer requests, wherein the states of the request queue can be outputted and information held in the request queue can be cleared.

Abstract: An extrusion-molded portion in the upper side portion of a weather strip is provided with a main seal member, a sub-seal member and a coupling portion. The main seal member has a first fitting base portion in the form of a substantially flat plate fitted to the first retainer of a door frame, and a hollow seal portion formed integrally with the first fitting base portion. The sub-seal member has a second fitting base portion in the form of a substantially flat plate fitted to a second retainer, and a seal lip. The seal lip, the coupling portion and the hollow seal portion are consecutively formed by monolithic molding with EPDM sponge rubber. The greater part of the second fitting base portion and the central part of the first fitting base portion are formed of EPDM solid rubber. Therefore, the difference in expansion rate hardly occurs and a warp is restrained from being generated.

Abstract: A semiconductor integrated circuit device has first and second receivers and first and second transmitters. The first receiver has a first clock data recovery (CDR) circuit, and the second receiver has a second CDR circuit. Each of these first and second CDR circuits receives serial data, recovers a clock from the received serial data, and changes the phase of the generated clock. The first transmitter has a first serializer (SER), and the second transmitter has a second SER. The first SER converts parallel data into serial data synchronized with a transmit clock or the clock generated by the first CDR circuit. The second SER converts parallel data into serial data synchronized with a transmit clock or the clock generated by the second CDR circuit.

Abstract: A synchronous circuit according to an embodiment of the present invention, comprising: a clock selector configured to select a suitable phase clock signal from a plurality of clock signals differing in phase from each other in accordance with a clock-selecting signal; a phase comparator configured to compare a phase of input data with that of the selected clock signal; a phase control circuit configured to generate a phase control signal in accordance with the comparison result obtained by the phase comparator and to generate the clock-selecting signal in accordance with a offset control signal; and a frequency offset control circuit configured to generate the offset control signal in accordance with the phase control signal.

Abstract: A semiconductor device including a port circuit (301) connected to an internal circuit, external terminals to which the port circuit is connected and a boundary scanning circuit (180, 18), the boundary scanning circuit being the one that makes access to the external terminals through the test access terminals. The test access terminals are also used as predetermined external terminals among the external terminals. Selection means (301, 303 to 307) are provided for selectively determining whether the multi-use terminals (P1 to P5) be connected to the port circuit or to the boundary scanning circuit, and for selecting, as an initial state, the state where the multi-use terminals are connected to the boundary scanning circuit in response to the power-on reset. Since the test access terminals need not be dedicated, the boundary scanning function can be furnished while guaranteeing pin compatibility of external terminals.

Abstract: A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC.

Abstract: A synchronous circuit according to an embodiment of the present invention, comprising:

Abstract: Methods of operating an instruction cache memory in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in a memory space. The entries of the instruction cache memory include a number of sets (nsets), where each of the sets comprise a number of ways (nways). One or more first instructions may be executed to load one or more instructions into a first way of the instruction cache memory. One or more second instructions may be executed to lock the first way of the instruction cache memory. A sequence of instructions may be executed including the one or more instructions loaded in the first way of the instruction cache memory, and it may be predetermined that the one or more instructions loaded in the first way of the instruction cache memory will executed without retrieving the one or more instructions from the memory during execution of the sequence of instructions.

Abstract: A comparator having a hit signal that is high, before a hit check is established in each way of an address array, and that goes low, when a mishit has been established. When a clock frequency is high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check is established. When the hit check has been established, data read from a way which has the hit is output onto a data line and an operation in the way which has a mishit is stopped.

Abstract: The engine compartment structure has an engine compartment and an engine unit. The engine compartment has side members, a rear cross member, and a steering rack mounted on the rear cross member. The engine unit has an engine, a transfer case, and a transaxle. The transfer case has an output shaft. The center of the output shaft is positioned lower than the center of an axle of transaxle. The steering rack is positioned lower than the output shaft. With this engine compartment structure, the height of a floor tunnel which houses a propeller shaft can be lowered. Also, the cross sectional height of the side members can be increased.

Abstract: Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted.

Abstract: In a floating point execution unit capable of executing arithmetic operation at high speed, a canceling prediction circuit (60) inputs directly operands before processing of selectors (2 and 3) and predicts a canceling generated in a subtraction result of the operands executed by a subtraction unit (5). The canceling prediction circuit (60) performs the canceling prediction without waiting the completion of carry adjustment of the operands executed by selecting and then executing the selectors (2 and 3). In addition, the prediction error detection circuit (100). Accordingly, when the subtraction result of the subtraction circuit (5) is output through a selector (12), or before the subtraction result is output, the canceling prediction can be executed. Thereby, the left shifter (8) can execute normalization operation for the subtraction result.