Abstract: An information processing apparatus comprising a secure information unit that is set to the state not requiring security in the case where the data is transferred from a user memory space to a general purpose register, and that is set to the state requiring security in the case where the data is transferred from a secure memory space to the general purpose register. An encryption key in the secure memory space is prevented from being stolen by prohibiting the data transfer to the user memory space from the general purpose register with the value of the secure information unit set to the state requiring security.

Abstract: A processor which can reduce delays occurring between the memory and the register file, and operate with a high operating frequency is provided. The processor 100 includes a register file 110 having plural registers, and a tag value generation circuit 102 which generates a tag value indicating data attributes. Each of the registers has a data field 112 for holding data, and a tag field 111 for holding a tag value. When executing a load instruction for loading data into a register of the register file 110 from the memory 14, the tag value generation circuit 102 generates a tag value in accordance with the load instruction and stores the generated tag value in the tag field 111.

Abstract: An information processing apparatus is disclosed, in which the value of a secure information unit is set to the state not requiring security in the case where the data is transferred from a user memory space to a general purpose register, and the value of the secure information unit is set to the state requiring security in the case where the data is transferred from a secure memory space to the general purpose register. An encryption key in the secure memory space is prevented from being stolen by prohibiting the data transfer to the user memory space from the general purpose register with the value of the secure information unit set to the state requiring security.