Abstract: An accelerator includes an interface configured to receive an instruction sequence including a plurality of instructions; a hierarchical memory configured to perform data transfer between a plurality of zeroth memories and a plurality of first memories according to a data transfer instruction specifically for data transfer between the plurality of zeroth memories and the plurality of first memories included in the instruction sequence received by the interface, the hierarchical memory including the plurality of zeroth memories, the plurality of first memories, and one or more second memories, each of the one or more second memories being connected to corresponding first memories among the plurality of first memories, and each of the plurality of first memories being connected to corresponding zeroth memories among the plurality of zeroth memories; and a plurality of arithmetic operators configured to operate in parallel by using the hierarchical memory.

Abstract: A compiler device, for generating an instruction sequence to be executed by an arithmetic processing device, includes at least one memory and at least one processor. The at least one processor is configured to receive a first instruction sequence for a first process and a second instruction sequence for a second process to be executed after the first process; generate third instructions, each third instruction being generated by merging a first instruction included in the first instruction sequence and a second instruction included in the second instruction sequence; and generate a third instruction sequence by concatenating the third instructions, instructions included in the first instruction sequence that are not merged into the third instructions, and instructions other than the second instruction among the plurality of instructions included in the second instruction sequence that are not merged into the one or more third instructions.

Abstract: A scheduling apparatus includes at least one memory and at least one processor, and the at least one processor is configured to generate a schedule from a state specified based on received information. The generating includes causing the state to transition such that a process of transferring data from a memory is replaced with a recomputation process that obtains the data.

Abstract: A compiler device, for generating an instruction sequence to be executed by an arithmetic processing device, includes at least one memory and at least one processor. The at least one processor is configured to receive a first instruction sequence for a first process and a second instruction sequence for a second process to be executed after the first process; generate third instructions, each third instruction being generated by merging a first instruction included in the first instruction sequence and a second instruction included in the second instruction sequence; and generate a third instruction sequence by concatenating the third instructions, instructions included in the first instruction sequence that are not merged into the third instructions, and instructions other than the second instruction among the plurality of instructions included in the second instruction sequence that are not merged into the one or more third instructions.