Abstract: According to one embodiment, a liquid crystal device includes a first liquid crystal cell and a second liquid crystal cell. The first liquid crystal cell and the second liquid crystal cell each include a first strip electrode, a second strip electrode, a third strip electrode and a fourth strip electrode. The extension direction of the first strip electrode and the second strip electrode in the first liquid crystal cell is different from the extension direction of the first strip electrode and the second strip electrode in the second liquid crystal cell. The extension direction of the first strip electrode and the second strip electrode intersects with the extension direction of the third strip electrode and the fourth strip electrode at an angle other than 90°.

Abstract: An information providing system 100 of the present invention includes an acquisition means 121 for acquiring disaster information and acquiring user information that is information related to a user, a generation means 122 for, on the basis of the disaster information and the user information, generating provided information including a captured image that is an image obtained by capturing a predetermined place, and a providing means 123 for providing an information processing device of the user with the provided information.

Abstract: A memory interface circuit, which controls capture timing of data provided from a memory according to a strobe signal provided from the memory, includes a control unit that controls an activation timing of an internal strobe gate signal, which masks the strobe signal when being deactivated, by delaying the internal strobe gate signal by a first period shorter than one cycle time of a clock signal to generate an internal strobe gate adjustment signal, and by adjusting an activation timing of the adjustment signal. A detection unit outputs a detection signal, when the strobe signal changes from a first potential to a second potential higher than the first potential, or when the first potential of the strobe signal continues for a second period or longer. The control unit adjusts the activation timing of the adjustment signal in accordance with the detection signal.

Abstract: A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts the output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal.

Abstract: A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal.

Abstract: A memory interface circuit, which controls capture timing of data provided from a memory according to a strobe signal provided from the memory, includes a control unit that controls an activation timing of an internal strobe gate signal, which masks the strobe signal when being deactivated, by delaying the internal strobe gate signal by a first period shorter than one cycle time of a clock signal to generate an internal strobe gate adjustment signal, and by adjusting an activation timing of the adjustment signal. A detection unit outputs a detection signal, when the strobe signal changes from a first potential to a second potential higher than the first potential, or when the first potential of the strobe signal continues for a second period or longer. The control unit adjusts the activation timing of the adjustment signal in accordance with the detection signal.

Abstract: A memory controller device coupled to a memory device equipment including a plurality of memory devices, includes a memory controller configured to instruct read-out of data in the memory device and a physical part configured to terminate a read-out signal for a certain period containing an arrival time of data read out from one memory device of the memory device equipment in accordance with a read-out instruction from the memory controller and excludes a part of a delay time from the read-out instruction until the data read-out of at least one other memory device.

Abstract: To provide a semiconductor module and a semiconductor device enabling more accurate testing of the connection state of the internal wiring between the semiconductor devices. The semiconductor device has switches SW11 through SW13 that connect a test terminal TT to one end side of wires to be tested, and transistors M21 through M23 that supply a ground potential VSS to the other end side of the wires to be tested. When a power source potential VDD is supplied to one end of the wires to be tested and a ground potential VSS is supplied to the other end of the wires to be tested, a current path can be formed including the wires to be tested. If a power source potential VDD is supplied to the wires to be tested and a ground potential VSS is supplied to the wires which are not to be tested, a difference in potential can be generated between the wires to be tested and the rest of the wires, which makes it possible to detect a short circuit failure.

Abstract: A memory controller device coupled to a memory device equipment including a plurality of memory devices, includes a memory controller configured to instruct read-out of data in the memory device and a physical part configured to terminate a read-out signal for a certain period containing an arrival time of data read out from one memory device of the memory device equipment in accordance with a read-out instruction from the memory controller and excludes a part of a delay time from the read-out instruction until the data read-out of at least one other memory device.

Abstract: To provide a semiconductor module and a semiconductor device enabling more accurate testing of the connection state of the internal wiring between the semiconductor devices. The semiconductor device has switches SW11 through SW13 that connect a test terminal TT to one end side of wires to be tested, and transistors M21 through M23 that supply a ground potential VSS to the other end side of the wires to be tested. When a power source potential VDD is supplied to one end of the wires to be tested and a ground potential VSS is supplied to the other end of the wires to be tested, a current path can be formed including the wires to be tested. If a power source potential VDD is supplied to the wires to be tested and a ground potential VSS is supplied to the wires which are not to be tested, a difference in potential can be generated between the wires to be tested and the rest of the wires, which makes it possible to detect a short circuit failure.

Abstract: According to one aspect of an embodiment of the present invention, there is provided a memory interface circuit including a first data output circuit which outputs a data signal based on a data strobe signal, the memory interface circuit comprising: a first delay-locked loop circuit that adjusts a delay of the data strobe signal and outputs the data strobe signal at a first timing; and a second data output circuit that outputs the data signal at a second timing different from the first timing during a normal operation, and outputs the data signal at the first timing during a test operation.

Abstract: A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape of the memory array. An address map changing unit is operatively coupled to the memory array, for receiving a first address signal for generating the first address and a second address signal for generating the second address. The address map changing unit is capable of changing the logical address map by altering a part of one of the first address signal and the second address signal.

Abstract: A memory device for ensuring efficient access and reduction in current consumption. The memory device includes a plurality of memory cells arranged in accordance with a first address and a second address which define a logical address map indicating a logical shape of the memory array. An address map changing unit is operatively coupled to the memory array, for receiving a first address signal for generating the first address and a second address signal for generating the second address. The address map changing unit is capable of changing the logical address map by altering a part of one of the first address signal and the second address signal.

Abstract: A method for controlling an input circuit of a synchronous semiconductor memory device that reduces current consumption without changing commands or increasing signal input terminals. The synchronous semiconductor memory device includes an input circuit for receiving write data and is operated based on a synchronizing signal. When the synchronous semiconductor memory device is active, the input circuit is selectively inactivated based on a mask control signal, which masks the write data. When the synchronous semiconductor memory device enters a write mode in which the synchronous semiconductor memory device stores data, the input circuit is activated and the mask control signal is invalidated.

Abstract: The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode, and during testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size.

Abstract: The present invention provides a semiconductor memory device for storing data. The semiconductor memory device performs data masking without increasing power consumption regardless of latency. The device includes a data output circuit for receiving and outputting the stored data. A mask signal input circuit receives a mask signal used to mask the data output from the data output circuit and provides the mask signal to the data output circuit. An input control circuit generates an activation signal that activates the mask signal input circuit and provides the activation signal to the mask signal input circuit. The input control circuit generates the activation signal based on a mode setting signal and a latency determination signal. The mode setting signal is used to activate the mask signal input circuit and set an operation mode of the semiconductor memory device. The latency determination signal has a level corresponding to latency information.

Abstract: A compact synchronous semiconductor device having an improved set-up/hold time is disclosed. A decoder receives input signals and generates decoded signals. A delay-adjusting unit adjusts the delay time of each of the decoded signals and provides adjusted decoded signals. A latch circuit unit latches the adjusted decoded signals in synchronism with a clock signal.

Abstract: A compact synchronous semiconductor device having an improved set-up/hold time is disclosed. A decoder receives input signals and generates decoded signals. A delay-adjusting unit adjusts the delay time of each of the decoded signals and provides adjusted decoded signals. A latch circuit unit latches the adjusted decoded signals in synchronism with a clock signal.

Abstract: A method for controlling an input circuit of a synchronous semiconductor memory device that reduces current consumption without changing commands or increasing signal input terminals. The synchronous semiconductor memory device includes an input circuit for receiving write data and is operated based on a synchronizing signal. When the synchronous semiconductor memory device is active, the input circuit is selectively inactivated based on a mask control signal, which masks the write data. When the synchronous semiconductor memory device enters a write mode in which the synchronous semiconductor memory device stores data, the input circuit is activated and the mask control signal is invalidated.

Abstract: The present invention provides a semiconductor memory device for storing data. The semiconductor memory device performs data masking without increasing power consumption regardless of latency. The device includes a data output circuit for receiving and outputting the stored data. A mask signal input circuit receives a mask signal used to mask the data output from the data output circuit and provides the mask signal to the data output circuit. An input control circuit generates an activation signal that activates the mask signal input circuit and provides the activation signal to the mask signal input circuit. The input control circuit generates the activation signal based on a mode setting signal and a latency determination signal. The mode setting signal is used to activate the mask signal input circuit and set an operation mode of the semiconductor memory device. The latency determination signal has a level corresponding to latency information.