Patents by Inventor Shinichiro Kobayashi
Shinichiro Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8833110Abstract: A washing machine includes a washing machine housing having electrical conducting properties and having an earth connection portion, a leaked water tub having electrical insulating properties and installed in a bottom part of the washing machine housing for accumulating leaked water, an electrode for detecting presence or absence of the leaked water in the leaked water tub, a leaked water detection circuit connected to the electrode, the leaked water detection circuit having an electrical insulating function, a retaining member having electrical insulating properties and retaining the electrode, and an attachment member having electrical conducting properties and attaching the electrode to the washing machine housing via the retaining member. The attachment member is electrically connected to the washing machine housing. In the leaked water tub, a lowest end of the attachment member is positioned on the lower side of a lowest end of the electrode. Thereby, a safe and inexpensive washing machine is realized.Type: GrantFiled: February 22, 2012Date of Patent: September 16, 2014Assignee: Panasonic CorporationInventors: Taketo Takahashi, Shinichiro Kobayashi
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Patent number: 8649360Abstract: A total of n signal processing circuits respectively constituted by independent circuit blocks process signals at the Data Link and Physical Layers. The signal processing circuits are associated with respective n groups of M/n subcarriers each, to process signals at the Data Link and Physical Layers. For example, the signal processing circuit independently processes signals of the subcarrier group at the Data Link and Physical Layers, the signal processing circuit independently processes signals of the subcarrier group at the Data Link and Physical Layers, and so on. The signal processing circuit independently processes signals of the subcarrier group at the Data Link and Physical Layers.Type: GrantFiled: April 26, 2011Date of Patent: February 11, 2014Assignee: Fujitsu LimitedInventors: Shinichiro Kobayashi, Hideo Kato, Yoshihisa Nakayama
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Patent number: 8553751Abstract: A radio equipment controller includes a calculator that calculates a delay amount by subtracting from a given maximum delay amount an internal delay amount of a radio equipment and a delay amount of a cable, the radio equipment modulating and transmitting orthogonal frequency division multiplexing (OFDM) symbols, and the cable connecting the radio equipment and the radio equipment controller that creates the OFDM symbols, a detector that detects a beginning of the OFDM symbols from data that is inputted into a buffer that stores data of the OFDM symbols, and a delay controller that determines a transmission timing of the OFDM symbols so that the transmission timing of the beginning of the OFDM symbols becomes a timing that is delayed by the calculated delay amount after a reference signal with a specific period.Type: GrantFiled: March 1, 2012Date of Patent: October 8, 2013Assignee: Fujitsu LimitedInventor: Shinichiro Kobayashi
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Publication number: 20130252622Abstract: A radio base station providing a service to a radio terminal by using plural component carriers includes a scheduler preferentially allocating, to the radio terminal, one of the component carriers that has a transmission power dynamic range whose lower limit value is lower than lower limit values of transmission power dynamic ranges of a rest of the component carriers; and a transmitter transmitting a radio signal to the radio terminal by using the allocated component carrier.Type: ApplicationFiled: December 16, 2012Publication date: September 26, 2013Applicant: FUJITSU LIMITEDInventor: Shinichiro KOBAYASHI
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Publication number: 20130125596Abstract: A front-loading-type washing machine of the invention includes a rotary drum; a water tub; a motor; a filter case that communicates with the water tub via a drain pipe connected to the bottom of the water tub and has a filter provided therein; a circulating pump that communicates with the filter case via a circulating water suction pipe connected to the filter case; a channel that communicates with the circulating pump via a circulating water discharge pipe connected to the circulating pump, and is formed on the front inner side of the water tub; a plurality of jetting ports that are provided on the inner peripheral side of the channel and discharge washing water into the water tub; and a control device. The opening area of the jetting port provided at the farthest position from a connecting portion between the circulating water discharge pipe and the channel is larger than the opening area of the jetting port provided at the nearest position from the connecting portion.Type: ApplicationFiled: February 22, 2012Publication date: May 23, 2013Applicant: PANASONIC CORPORATIONInventors: Hideaki Ushijima, Yutaka Inoue, Shinichiro Kobayashi, Masahiro Itami
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Publication number: 20130055768Abstract: A washing machine includes a washing machine housing having electrical conducting properties and having an earth connection portion, a leaked water tub having electrical insulating properties and installed in a bottom part of the washing machine housing for accumulating leaked water, an electrode for detecting presence or absence of the leaked water in the leaked water tub, a leaked water detection circuit connected to the electrode, the leaked water detection circuit having an electrical insulating function, a retaining member having electrical insulating properties and retaining the electrode, and an attachment member having electrical conducting properties and attaching the electrode to the washing machine housing via the retaining member. The attachment member is electrically connected to the washing machine housing. In the leaked water tub, a lowest end of the attachment member is positioned on the lower side of a lowest end of the electrode. Thereby, a safe and inexpensive washing machine is realized.Type: ApplicationFiled: February 22, 2012Publication date: March 7, 2013Applicant: PANASONIC CORPORATIONInventors: Taketo Takahashi, Shinichiro Kobayashi
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Publication number: 20130014546Abstract: A drum-type washing machine includes left and right side plates formed of steel plates, the side plates defining side surfaces of an outer case, a front cover provided with an openable and closable door, the front cover defining a front surface of the outer case, an upper cover defining an upper surface of the outer case, a water tank oscillatably arranged in the outer case, and a rotary drum axially supported in the water tank, wherein a plurality of concave portions are formed on the left and right side plates, and the concave portion closer to the front surface of the outer case as a door side has an arc shape with a larger curvature. Thus, rigidity of the side plates in the up and down direction and the left and right direction is increased, so that vibration at the time of spin-drying is reduced.Type: ApplicationFiled: February 15, 2012Publication date: January 17, 2013Applicant: Panasonic CorporationInventors: Shinichiro Kobayashi, Yutaka Inoue, Masahiro Itami, Hideaki Ushijima
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Publication number: 20120236916Abstract: A radio equipment controller includes a calculator that calculates a delay amount by subtracting from a given maximum delay amount an internal delay amount of a radio equipment and a delay amount of a cable, the radio equipment modulating and transmitting orthogonal frequency division multiplexing (OFDM) symbols, and the cable connecting the radio equipment and the radio equipment controller that creates the OFDM symbols, a detector that detects a beginning of the OFDM symbols from data that is inputted into a buffer that stores data of the OFDM symbols, and a delay controller that determines a transmission timing of the OFDM symbols so that the transmission timing of the beginning of the OFDM symbols becomes a timing that is delayed by the calculated delay amount after a reference signal with a specific period.Type: ApplicationFiled: March 1, 2012Publication date: September 20, 2012Applicant: FUJITSU LIMITEDInventor: Shinichiro KOBAYASHI
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Publication number: 20120099570Abstract: A total of n signal processing circuits respectively constituted by independent circuit blocks process signals at the Data Link and Physical Layers. The signal processing circuits are associated with respective n groups of M/n subcarriers each, to process signals at the Data Link and Physical Layers. For example, the signal processing circuit independently processes signals of the subcarrier group at the Data Link and Physical Layers, the signal processing circuit independently processes signals of the subcarrier group at the Data Link and Physical Layers, and so on. The signal processing circuit independently processes signals of the subcarrier group at the Data Link and Physical Layers.Type: ApplicationFiled: April 26, 2011Publication date: April 26, 2012Applicant: FUJITSU LIMITEDInventors: Shinichiro KOBAYASHI, Hideo KATO, Yoshihisa NAKAYAMA
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Patent number: 7795931Abstract: An operational comparator 10 includes a current source circuit, load circuits driven by the current source circuit, and a current mirror circuit. The load circuits are constituted with MOS transistors, predetermined reference voltage is supplied to the gate terminals of MOS transistors, and each of signal voltages constituting the differential output signal of the differential output circuit is supplied to gate of MOS transistors.Type: GrantFiled: December 12, 2008Date of Patent: September 14, 2010Assignee: Seiko Epson CorporationInventor: Shinichiro Kobayashi
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Patent number: 7745559Abstract: An integrated circuit device includes: an internal circuit disposed on an inside area of the integrated circuit device; and at least one regulator circuit that generates a regulation voltage formed by stepping down a power supply voltage provided from outside, wherein an output terminal of the regulator circuit is connected to a first pad that is an external terminal of the integrated circuit device and a power supply line of the internal circuit, and the regulator circuit controls the state of the output terminal based on a plurality of control signals inputted respectively to a plurality of control terminals.Type: GrantFiled: August 29, 2007Date of Patent: June 29, 2010Assignee: Seiko Epson CorporationInventor: Shinichiro Kobayashi
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Publication number: 20090153199Abstract: An operational comparator 10 includes a current source circuit, load circuits driven by the current source circuit, and a current mirror circuit. The load circuits are constituted with MOS transistors, predetermined reference voltage is supplied to the gate terminals of MOS transistors, and each of signal voltages constituting the differential output signal of the differential output circuit is supplied to gate of MOS transistors.Type: ApplicationFiled: December 12, 2008Publication date: June 18, 2009Applicant: SEIKO EPSON CORPORATIONInventor: Shinichiro Kobayashi
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Publication number: 20090072880Abstract: An output circuit group comprises at least one first output circuit that outputs a pair of differential signals, the first output circuit including a first reversing circuit operated by applying a first power supply potential and a second power supply potential to reverse a first driving signal so as to output a first reverse driving signal, a first signal level converting circuit operated by applying the first power supply potential and a third power supply potential to convert the first driving signal to a signal having a predetermined level to output, a second signal level converting circuit operated by applying the first and the third power supply potentials to convert the first reverse driving signal to a signal having a predetermined level to output, a first differential circuit operated by applying the first and the third power supply potentials to output a signal having a first polarity corresponding to a difference between the signal output from the first signal level converting circuit and the signaType: ApplicationFiled: July 11, 2008Publication date: March 19, 2009Applicant: SEIKO EPSON CORPORATIONInventor: Shinichiro KOBAYASHI
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Patent number: 7489899Abstract: A method is provided for building an information network via an antenna terminal or an antenna cable disposed in a house for receiving television broadcasting or radio broadcasting. The method comprises step (a) of selecting at least one frequency not used by television broadcasting or radio broadcasting in an area where the house is located; step (b) of modulating a carrier wave having the frequency selected in step (a) by using transmission data transmitted from a first information terminal and transmitting the modulated carrier wave via the antenna terminal or the antenna cable; and step (c) of receiving the carrier wave transmitted in step (b) and demodulating the carrier wave to produce reception data received by a second information terminal.Type: GrantFiled: January 8, 2004Date of Patent: February 10, 2009Assignee: Seiko Epson CorporationInventors: Shinichiro Kobayashi, Toshifumi Yamakawa
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Patent number: 7475781Abstract: A package is presented from which contents can be easily taken out. This package includes a film with a soft packaging material. On the surface of the soft packaging material is a cut line, such that, inside the cut line, an openable region is formed for taking contents out from the package. Further, inside the openable region, dashed lines are provided. When a lid member adhering to cover the openable region is peeled, the openable region easily adheres to the lid member side owing to the dashed lines to reliably form the opened portion.Type: GrantFiled: June 16, 2005Date of Patent: January 13, 2009Assignee: Uni-Charm CorporationInventors: Shinichiro Kobayashi, Ikuya Saito, Sachi Sugiura
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Publication number: 20090002044Abstract: A master-slave type flip-flop circuit consisting of a master latch and a slave latch, wherein the master latch comprises: a first clocked inverter to which data are input and a first latch circuit configuring a closed circuit with a first inverter and a second clocked inverter so that an output of the first clocked inverter is input to the first inverter and; the slave latch comprises: a transmission gate to which an output from the first latch circuit is input and a second latch circuit configuring a closed circuit with a second inverter and a third clocked inverter so that an output of the transmission gate is input to the second inverter, respective components configuring the master latch and the slave latch are configured with Sea Of Gate (hereinafter to be referred to as SOG) configuring a gate array, a basic cell of the SOG consists of triplely arrayed N-type transistors and corresponding triplely arrayed P-type transistors, the triplely arrayed N-type transistors consist of double-arrayed normally sizeType: ApplicationFiled: June 20, 2008Publication date: January 1, 2009Applicant: SEIKO EPSON CORPORATIONInventor: Shinichiro Kobayashi
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Publication number: 20080284471Abstract: A current load driving circuit for driving a current load, including: a first current mirror circuit that outputs a current; and a second current mirror circuit that receives the current outputted from the first current mirror circuit as an input current and then amplifies the input current to drive the current load. The whole of the first current mirror circuit and the second current mirror circuit is divided into an input circuit and an output circuit; and the divided position is provided on a voltage route of the first current mirror circuit or a voltage route of the second current mirror circuit.Type: ApplicationFiled: May 13, 2008Publication date: November 20, 2008Applicant: SEIKO EPSON CORPORATIONInventor: Shinichiro Kobayashi
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Patent number: 7399610Abstract: The present invention provides a simple cell-free protein synthesis method capable of affording synthesis of a protein in a high amount in a short time at a low cost. A method for cell-free protein synthesis using an extract derived from an insect cell, the method comprising removing a component which can pass through a semipermeable membrane through the semipermeable membrane while maintaining synthesis reaction, thereby to continuously synthesize a protein. Preferably, an mRNA is additionally supplied while said synthesis reaction is maintained. Further, said insect cell is preferably an established culture cell derived from Trichoplusia ni ovum cell.Type: GrantFiled: October 12, 2005Date of Patent: July 15, 2008Assignee: Shimadzu CorporationInventors: Masamitsu Shikata, Nobuhiro Hanafusa, Shinichiro Kobayashi
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Publication number: 20080054872Abstract: An integrated circuit device includes: an internal circuit disposed on an inside area of the integrated circuit device; and at least one regulator circuit that generates a regulation voltage formed by stepping down a power supply voltage provided from outside, wherein an output terminal of the regulator circuit is connected to a first pad that is an external terminal of the integrated circuit device and a power supply line of the internal circuit, and the regulator circuit controls the state of the output terminal based on a plurality of control signals inputted respectively to a plurality of control terminals.Type: ApplicationFiled: August 29, 2007Publication date: March 6, 2008Applicant: SEIKO EPSON CORPORATIONInventor: Shinichiro KOBAYASHI
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Publication number: 20080048627Abstract: A regulator circuit for generating a regulation voltage obtained by stepping down a power supply voltage includes a plurality of voltage generation circuits that each generate a reference voltage; a differential amplifier circuit to whose first input terminal a reference voltage generated by one of the voltage generation circuits is inputted, to whose second input terminal the regulation voltage generated by the regulator circuit is inputted, and that amplifies a difference between the reference voltage and the regulation voltage; and an output circuit to which an output terminal of the differential amplifier circuit is coupled and that outputs the regulation voltage.Type: ApplicationFiled: July 11, 2007Publication date: February 28, 2008Applicant: SEIKO EPSON CORPORATIONInventor: Shinichiro KOBAYASHI